Patent attributes
An array substrate is disclosed. A gate line group, common electrode line and two adjacent data lines together defining a pixel unit which has: a thin film transistor; a first and second pixel electrode disposed between the gate line group and the common electrode line; a sharing capacitor disposed between the gate line group and the pixel electrodes. The pixel units are arranged in a plurality of rows along the extending direction of data line, two adjacent pixel units are arranged sequentially in opposite direction. By using each of the sharing capacitors of the adjacent pixel units, the light leakage regions will be away from the openings of the pixel electrodes, therefore the movable mura can be eliminated without increasing the width of the black matrix and the aperture ratio loss can be solved.
