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US Patent 9748206 Three-dimensional stacking structure and manufacturing method thereof
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Patent
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Date Filed
May 26, 2016
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Date of Patent
August 29, 2017
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Patent Application Number
15164883
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Patent Citations Received
US Patent 12125779 Semiconductor device
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US Patent 11670621 Die stack structure
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US Patent 11756901 Seal ring for hybrid-bond
US Patent 11876049 Bonding alignment marks at bonding interface
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US Patent 12087756 Protective wafer grooving structure for wafer thinning and methods of using the same
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Patent Inventor Names
Chaochieh Tsai
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Peter Yu Fei Huang
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
9748206
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Patent Primary Examiner
Julio J Maldonado
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