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US Patent 9753895 Method for process variation analysis of an integrated circuit

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Is a
Patent
Patent
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Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
97538950
Patent Inventor Names
Kmin Hsu0
Wei-Yi Hu0
Chin-Cheng Kuo0
Jui-Feng Kuan0
Wei Min Chan0
Date of Patent
September 5, 2017
0
Patent Application Number
148183490
Date Filed
August 5, 2015
0
Patent Citations Received
‌
US Patent 11774498 Multi-rate sampling for hierarchical system analysis
Patent Primary Examiner
‌
Nghia Doan
0
Patent abstract

A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

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