Patent attributes
A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.
