US Patent 9767910 Semiconductor memory device and memory system

A semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including fifth to eighth memory cells; a first word line coupled to gates of the first and fifth memory cells; a second word line coupled to gates of the second and sixth memory cells; a third word line coupled to gates of the third and seventh memory cells; and a fourth word line coupled to gates of the fourth and eighth memory cells. In a write operation, writes to the fourth memory cell, the first memory cell, the eighth memory cell, and the fifth memory cell are executed in order.