US Patent 9793156 Self-aligned low resistance metallic interconnect structures

Methods are provided for fabricating self-aligned, low resistance metal interconnect structures, as well as semiconductor devices comprising such metal interconnect structures. A first metal line is formed in a first insulating layer. An etch stop layer is formed by selectively depositing dielectric material on the first insulating layer. A second insulating layer is formed over the etch stop layer and the first metal line, and an opening is etched in the second insulating layer selective to the etch stop layer to prevent etching of the first insulating layer. The opening is filled with a metallic material to form a second metal line in contact with the first metal line. The first and second metal lines are formed with aspect ratios that are less than 2.5 to minimize resistivity of the metal lines. The first and second metal lines collectively form a single metal line of an interconnect structure.