Patent attributes
Analog-to-digital conversion circuitry for generating a digital output signal is disclosed comprising a sample-and-hold circuit comprising an adjustable sample capacitor for coupling to an analog input signal during a sample phase, and an analog-to-digital converter (ADC) coupled to an output of the sample-and-hold circuit during a hold phase. In order to compensate in real-time for an increase in an amplitude of the input signal, a capacitance of the sample capacitor is decreased by an attenuation factor, and an output of the ADC is multiplied by an inverse of the attenuation factor to generate the digital output signal.