US Patent 9813227 At-rate SERDES clock data recovery with controllable offset
Patent 9813227 was granted and assigned to Oracle on November, 2017 by the United States Patent and Trademark Office.
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Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.
US Patent 09813227 At-rate SERDES clock data recovery with controllable offset US Patent 9813227 At-rate SERDES clock data recovery with controllable offset
US Patent 09813227 At-rate SERDES clock data recovery with controllable offset
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