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US Patent 9825779 Network-on-chip (NoC) topology generation

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
May 26, 2015
Date of Patent
November 21, 2017
Patent Application Number
14722046
Patent Citations Received
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US Patent 12135928 Constraints and objectives used in synthesis of a network-on-chip (NoC)
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US Patent 11836427 Constraints and objectives used in synthesis of a network-on-chip (NoC)
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US Patent 11956127 Incremental topology modification of a network-on-chip
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US Patent 12067335 Automatic configuration of pipeline modules in an electronics system
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US Patent 11657203 Multi-phase topology synthesis of a network-on-chip (NoC)
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US Patent 11665776 System and method for synthesis of a network-on-chip for deadlock-free transformation
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US Patent 11675942 Optimization of parameters for synthesis of a topology using a discriminant function module
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US Patent 11748535 System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
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US Patent 11784909 Quality metrics for optimization tasks in generation of a network
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US Patent 11838211 System and method to determine optimal path(s) and use load balancing in an interconnect
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9825779
Patent Primary Examiner
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Alvin Zhu

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