Patent attributes
An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.
