Patent attributes
A data storage device includes a semiconductor structure including a first conductive-type region having a first-type conductivity, a second conductive-type region spaced apart from the first conductive-type region and having a second-type conductivity opposite to the first-type conductivity, and a semiconductor region between the first conductive-type region and the second conductive-type region and including a neighboring portion adjacent to the second conductive-type region; a mode select transistor including a gate electrode aligned with the neighboring portion and an insulation layer between the gate electrode and the neighboring portion; a plurality of memory cell transistors including a plurality of control gate electrodes aligned with the semiconductor region, and a data storage layer interposed between the plurality of control gate electrodes and the semiconductor region; a first wire electrically connected to the first conductive-type region; and a second wire including an ambipolar contact having a first contact between the second wire and the second conductive-type region, and a second contact between the second wire and the neighboring portion.
