US Patent 9864699 Method and apparatus for compressing LUT

Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.