US Patent 9871140 Dual strained nanosheet CMOS and methods for fabricating

A method includes: growing a lattice of alternating sheets of tensile strained silicon and relaxed silicon-germanium on a substrate; isolating a first portion of the lattice from a second portion of the lattice; forming source regions and drain regions on each of the first portion of the lattice and the second portion of the lattice; forming a first gate opening in the first portion of the lattice and a second gate opening in the second portion of the lattice; selectively removing the sheets of relaxed silicon-germanium from under the second gate opening in the second portion of the lattice; selectively removing portions of the sheets of tensile strained silicon from under the first gate opening in the first portion of the lattice; and increasing a germanium content in the relaxed silicon-germanium layers under the first gate opening in the first portion of the lattice.