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US Patent 9882703 Resolving meta-stability in a clock and data recovery circuit

Patent 9882703 was granted and assigned to Xilinx on January, 2018 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Xilinx
Xilinx
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Current Assignee
Xilinx
Xilinx
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
98827030
Patent Inventor Names
Alan C. Wong0
Winson Lin0
Yohan Frans0
Yu Xu0
Caleb S. Leung0
Christopher J. Borrelli0
Kun-Yung Chang0
Date of Patent
January 30, 2018
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Patent Application Number
153464340
Date Filed
November 8, 2016
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Patent Citations Received
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US Patent 12126381 Optimal equalization partitioning
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US Patent 12063129 Frequency detector for clock data recovery
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Patent Primary Examiner
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Khanh C Tran
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Patent abstract

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

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