Patent attributes
An apparatus includes a processor and storage to store instructions that cause the processor to perform operations including: receive an indication of completion of a first task with a first partition such that the first node device is available to assign to perform another task; delay assignment of performance of a second task on a second partition to the first node device for up to a predetermined period of time, in spite of readiness of the second task to be performed on the second partition and availability of the first node device; determine whether an indication of completion of the first task with the second partition such that the second node device is available to assign to perform another task is received within the predetermined period of time; and assign performance of the second task on the second partition to the second node device based on the determination.
