Patent attributes
To provide a semiconductor device including a first memory cell for holding first analog data, a second memory cell for holding reference analog data, and an offset circuit. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is supplied. The offset circuit supplies a third current corresponding to a differential current between the first current and the second current. The first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is supplied. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained. By providing a plurality of product-sum operation circuits that can be freely connected, a hierarchical neural network can be formed.
