US Patent 9934838 Pulse shaping unit cell and array for symmetric updating

A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric weight updating for a given state update in response to an input pulse and state feedback. The memory unit further includes a synapse element having a memory element with hysteresis for storing one of multiple possible states responsive to the adjusted pulse and for providing the state feedback to the pulse adjustment circuit.