US Patent 9972495 Low-K dielectric spacer for a gate cut

Structures including one or more field-effect transistors and methods for forming a structure that includes one or more field-effect transistors. A first semiconductor fin and a second semiconductor fin are formed in which the second semiconductor fin is spaced from the first semiconductor fin. A semiconductor layer is formed that covers the first semiconductor fin and the second semiconductor fin. An opening is formed in the semiconductor layer that exposes the first semiconductor fin. A dielectric spacer is formed on at least one sidewall of the semiconductor layer bordering the opening.