US Patent 9990969 Page buffer and memory device including the same

Provided herein are a page buffer and a memory device having the same. The page buffer may include: a latch circuit comprising a first node configured to be set to a first level in response to a sense amplifier strobe signal when an operation of setting up a bit line is performed during a program operation of a semiconductor memory device; a current control circuit configured to supply an internal power to a current sensing node depending on a value of the first level of the first node; and a page buffer sensing circuit configured to couple the bit line to the current sensing node in response to a page buffer sensing signal and control a potential level of the bit line depending on a potential level of the page buffer sensing signal.