US Patent 9998125 Clock calibration using asynchronous digital sampling

Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.