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US Patent RE49821 Semiconductor integrated circuit
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Patent
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Date Filed
October 18, 2021
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Date of Patent
January 30, 2024
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Patent Application Number
17503860
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Patent Citations
US Patent RE48085 Semiconductor integrated circuit
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US Patent RE48831 Semiconductor integrated circuit
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US Patent 6838713 Dual-height cell with variable width power rail architecture
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US Patent 6980462 Memory cell architecture for reduced routing congestion
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US Patent 7129562 Dual-height cell with variable width power rail architecture
0
US Patent RE45988 Semiconductor integrated circuit
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US Patent RE47095 Semiconductor integrated circuit
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Patent Inventor Names
Yoshinori Tanaka
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
RE49821
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Patent Primary Examiner
Kenneth Whittington
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CPC Code
H01L 27/11807
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H01L 27/0207
0
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