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William M. Treat

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Edits on 7 Sep, 2022
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Felix Skowronek
Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7093110 Register file in the register window system and controlling method thereof
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US Patent 7100021 Barrier synchronization mechanism for processors of a systolic array
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US Patent 7103756 Data processor with individually writable register subword locations
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US Patent 7107432 VLIW processor with data spilling means
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US Patent 7111154 Method and apparatus for NOP folding
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US Patent 7117345 Non-stalling circular counterflow pipeline processor with reorder buffer
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US Patent 7127591 Instruction control device and method therefor
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US Patent 7130986 Determining if a register is ready to exchange data with a processing element
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US Patent 7134001 Pipeline replay support for unaligned memory operations
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US Patent 7136992 Method and apparatus for a stew-based loop predictor
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US Patent 7139900 Data packet arithmetic logic devices and methods
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US Patent 7143271 Automatic register backup/restore system and method
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US Patent 7146487 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
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US Patent 7146491 Apparatus and method for generating constant values
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US Patent 7149881 Method and apparatus for improving dispersal performance in a processor through the use of no-op ports
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US Patent 7152155 System and method of correcting a branch misprediction
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US Patent 7159102 Branch control memory
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US Patent 7162614 Elimination of potential renaming stalls due to use of partial registers
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US Patent 7162616 Floating point unit pipeline synchronized with processor pipeline
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US Patent 7178012 Semiconductor device
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US Patent 7181601 Method and apparatus for prediction for fork and join instructions in speculative execution
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US Patent 7188233 System and method for performing floating point store folding
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US Patent 7188234 Run-ahead program execution with value prediction
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US Patent 7194599 Configurable co-processor interface
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US Patent 7194607 Method and apparatus for command translation and enforcement of ordering of commands
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US Patent 7194608 Method, apparatus and computer program product for identifying sources of performance events
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US Patent 7194610 Processor and pipeline reconfiguration control method
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US Patent 7197628 Method and apparatus for execution flow synonyms
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US Patent 7200742 System and method for creating precise exceptions
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US Patent 7203826 Method and apparatus for managing a return stack
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US Patent 7210024 Conditional instruction execution via emissary instruction for condition evaluation
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US Patent 7237090 Configurable out-of-order data transfer in a coprocessor interface
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US Patent 7237094 Instruction group formation and mechanism for SMT dispatch
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US Patent 7237097 Partial bitwise permutations
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US Patent 7240183 System and method for detecting instruction dependencies in multiple phases
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US Patent 7249244 Data processing system
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US Patent 7254697 Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
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US Patent 7257696 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
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US Patent 7257698 Instruction buffer and method of controlling the instruction buffer where buffer entries are issued in a predetermined order
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US Patent 7260705 Apparatus to implement mesocode
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US Patent 7260709 Processing method and apparatus for implementing systolic arrays
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US Patent 7266674 Programmable delayed dispatch in a multi-threaded pipeline
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US Patent 7269715 Instruction grouping history on fetch-side dispatch group formation
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US Patent 7269720 Dynamically controlling execution of operations within a multi-operation instruction
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US Patent 7272705 Early exception detection
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US Patent 7275146 Instruction control device and method therefor
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US Patent 7284114 Video processing system with reconfigurable instructions
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US Patent 7287147 Configurable co-processor interface
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US Patent 7299369 Power reduction in microprocessor systems
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US Patent 7302555 Zero overhead branching and looping in time stationary processors
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US Patent 7310722 Across-thread out of order instruction dispatch in a multithreaded graphics processor
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US Patent 7313671 Processing apparatus, processing method and compiler
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US Patent 7313673 Fine grained multi-thread dispatch block mechanism
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US Patent 7313674 Instruction control device and method therefor
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US Patent 7313675 Register allocation technique
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US Patent 7315937 Microprocessor instructions for efficient bit stream extractions
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US Patent 7320062 Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
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US Patent 7320066 Branch predicting apparatus and branch predicting method
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US Patent 7334111 Method and related device for use in decoding executable code
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US Patent 7340628 Branch based activity monitoring
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US Patent 7353370 Method and apparatus for processing an event occurrence within a multithreaded processor
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US Patent 7356675 Data processor
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US Patent 7360064 Thread interleaving in a multithreaded embedded processor
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US Patent 7370178 Method for latest producer tracking in an out-of-order processor, and applications thereof
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US Patent 7389408 Microarchitecture for compact storage of embedded constants
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US Patent 7395409 Split embedded DRAM processor
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US Patent 7395414 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
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US Patent 7395415 Method and apparatus to provide a source operand for an instruction in a processor
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US Patent 7404096 Microprocessor for reducing leakage power and method thereof
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US Patent 7412591 Apparatus and method for switchable conditional execution in a VLIW processor
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US Patent 7430612 Computing apparatus, computing program, and computing method
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US Patent 7434039 Computer processor capable of responding with comparable efficiency to both software-state-independent and state-dependent events
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US Patent 7434898 Computer system, computer program, and addition method
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US Patent 7437534 Local and global register partitioning technique
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US Patent 7444501 Methods and apparatus for recognizing a subroutine call
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US Patent 7447887 Multithread processor
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US Patent 7454597 Computer processing system employing an instruction schedule cache
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US Patent 7457941 Vector processing system
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US Patent 7475224 Register map unit supporting mapping of multiple register specifier classes
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US Patent 7478226 Processing bypass directory tracking system and method
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US Patent 7478227 Apparatus and method for optimizing loop buffer in reconfigurable processor
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US Patent 7496732 Method and apparatus for results speculation under run-ahead execution
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US Patent 7506136 Parallel data processing apparatus
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US Patent 7506137 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
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US Patent RE40693 Method and apparatus for creating a wireframe and polygon virtual world
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US Patent 7512772 Soft error handling in microprocessors
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US Patent 7523446 User-space return probes
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US Patent 7526630 Parallel data processing apparatus
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US Patent 7529907 Method and apparatus for improved computer load and store operations
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US Patent 7546476 Power reduction in microprocessor systems
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US Patent 7558945 System and method for register renaming
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US Patent 7571300 Modular distributive arithmetic logic unit
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US Patent 7571305 Reusing a buffer memory as a microcache for program instructions of a detected program loop
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US Patent 7590832 Information processing device, compressed program producing method, and information processing system
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US Patent 7594097 Microprocessor output ports and control of instructions provided therefrom
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US Patent 7596781 Register-based instruction optimization for facilitating efficient emulation of an instruction stream
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US Patent 7606996 Array type operation device
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US Patent 7610475 Programmable logic configuration for instruction extensions
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US Patent 7617493 Defining memory indifferent trace handles
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US Patent 7620796 System and method for acceleration of streams of dependent instructions within a microprocessor
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US Patent 7620798 Latency tolerant pipeline synchronization
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US Patent 7624254 Segmented pipeline flushing for mispredicted branches
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US Patent 7627743 Method and circuit implementation for multiple-word transfer into/from memory subsystems
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US Patent 7647480 Handling of conditional instructions in a data processing apparatus
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US Patent 7647518 Replay reduction for power saving
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US Patent 7650486 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
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US Patent 7660974 Method and apparatus for analyzing performance, and computer product
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US Patent 7669039 Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction
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US Patent 7669040 Method and apparatus for executing a long transaction
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US Patent 7669041 Instruction-parallel processor with zero-performance-overhead operand copy
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US Patent 7676657 Across-thread out-of-order instruction dispatch in a multithreaded microprocessor
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US Patent 7681019 Executing functions determined via a collection of operations from translated instructions
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US Patent 7689815 Debug instruction for use in a data processing system
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US Patent 7698449 Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element
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US Patent 7698533 Configurable co-processor interface
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US Patent 7698594 Reconfigurable processor and reconfiguration method executed by the reconfigurable processor
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US Patent 7707388 Computer memory architecture for hybrid serial and parallel computing systems
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US Patent 7716454 Method and apparatus for matrix decomposition in programmable logic devices
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US Patent 7721077 Performing endian conversion
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US Patent 7725681 Parallel processing array
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US Patent 7725698 Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor
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US Patent 7730285 Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof
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US Patent 7734900 Computer configuration virtual topology discovery and instruction therefore
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US Patent 7747839 Data processing apparatus and method for handling instructions to be executed by processing circuitry
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US Patent 7747840 Method for latest producer tracking in an out-of-order processor, and applications thereof
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US Patent 7765389 Management of exceptions and hardware interruptions by an exception simulator
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US Patent 7774583 Processing bypass register file system and method
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US Patent 7779230 Data flow execution of methods in sequential programs
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US Patent 7779233 System and method for implementing a software-supported thread assist mechanism for a microprocessor
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US Patent 7779234 System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor
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US Patent 7779238 Method and apparatus for precisely identifying effective addresses associated with hardware events
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US Patent 7788471 Data processor and methods thereof
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US Patent 7797513 Non-blocking, multi-context pipelined processor
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US Patent 7802252 Method and apparatus for selecting the architecture level to which a processor appears to conform
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US Patent 7818540 Vector processing system
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US Patent 7844796 Data processing device and method
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US Patent 7853860 Programmable signal and processing circuit and method of depuncturing
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US Patent 7874009 Data processing device
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US Patent 7886129 Configurable co-processor interface
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US Patent 7886135 Pipeline replay support for unaligned memory operations
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US Patent 7890733 Processor memory system
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US Patent 7890740 Processor comprising a first and a second mode of operation and method of operating the same
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US Patent 7917735 Data processing apparatus and method for pre-decoding instructions
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US Patent 7917736 Latency tolerant pipeline synchronization
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US Patent 7925866 Data processing apparatus and method for handling instructions to be executed by processing circuitry
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US Patent 7925867 Pre-decode checking for pre-decoded instructions that cross cache line boundaries
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US Patent 7930686 Defining memory indifferent trace handles
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US Patent 7934081 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
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US Patent 7934082 Information processing apparatus and exception control circuit
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US Patent 7937566 Processing bypass directory tracking system and method
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US Patent 7958332 Parallel data processing apparatus
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US Patent RE42466 Branch predicting apparatus and branch predicting method
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US Patent 7966475 Parallel data processing apparatus
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US Patent 7975132 Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor
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US Patent 7979673 Method and apparatus for matrix decompositions in programmable logic devices
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US Patent 7979675 Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution
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US Patent 7979678 System and method for register renaming
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US Patent 7984275 Computer configuration virtual topology discovery and instruction therefore
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US Patent 7987340 Communications in a processor array
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US Patent 7996618 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
Edits on 8 Dec, 2021
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edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7987340 Communications in a processor array
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7984275 Computer configuration virtual topology discovery and instruction therefore
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7979673 Method and apparatus for matrix decompositions in programmable logic devices
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7979678 System and method for register renaming
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7966475 Parallel data processing apparatus
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Golden AI
edited on 7 Dec, 2021
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Infobox (+1 properties)
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Patent primary examiner of
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US Patent RE42466 Branch predicting apparatus and branch predicting method
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
‌
US Patent 7958332 Parallel data processing apparatus
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
‌
US Patent 7937566 Processing bypass directory tracking system and method
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7934082 Information processing apparatus and exception control circuit
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Golden AI
edited on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
‌
US Patent 7930686 Defining memory indifferent trace handles
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7925867 Pre-decode checking for pre-decoded instructions that cross cache line boundaries
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Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7917735 Data processing apparatus and method for pre-decoding instructions
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7917736 Latency tolerant pipeline synchronization

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