List of Atrenta patents

Patents where

Current Assignee

Name

Atrenta

Name	Description	Patent Applicant	Current Assignee	Patent Jurisdiction	Patent Number	Date of Patent
‌ US Patent 8930863 System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist	Patent 8930863 was granted and assigned to Atrenta on January, 2015 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8930863	January 6, 2015
‌ US Patent 7536662 Method for recognizing and verifying FIFO structures in integrated circuit designs	Patent 7536662 was granted and assigned to Atrenta on May, 2009 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	7536662	May 19, 2009
‌ US Patent 7451427 Bus representation for efficient physical synthesis of integrated circuit designs	Patent 7451427 was granted and assigned to Atrenta on November, 2008 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	7451427	November 11, 2008
‌ US Patent 7076748 Identification and implementation of clock gating in the design of integrated circuits	Patent 7076748 was granted and assigned to Atrenta on July, 2006 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	7076748	July 11, 2006
‌ US Patent 8739087 System and method for large multiplexer identification and creation in a design of an integrated circuit	Patent 8739087 was granted and assigned to Atrenta on May, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8739087	May 27, 2014
‌ US Patent 8448111 System and method for metastability verification of circuits of an integrated circuit	Patent 8448111 was granted and assigned to Atrenta on May, 2013 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	8448111	May 21, 2013
‌ US Patent 8745567 Efficient apparatus and method for analysis of RTL structures that cause physical congestion	Patent 8745567 was granted and assigned to Atrenta on June, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8745567	June 3, 2014
‌ US Patent 8656328 System and method for abstraction of a circuit portion of an integrated circuit	Patent 8656328 was granted and assigned to Atrenta on February, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8656328	February 18, 2014
‌ US Patent 8635578 System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption	Patent 8635578 was granted and assigned to Atrenta on January, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8635578	January 21, 2014
‌ US Patent 8984469 System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption	Patent 8984469 was granted and assigned to Atrenta on March, 2015 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8984469	March 17, 2015
‌ US Patent 8656335 System and methods for inferring higher level descriptions from RTL topology based on connectivity propagation	Patent 8656335 was granted and assigned to Atrenta on February, 2014 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	8656335	February 18, 2014
‌ US Patent 8732647 Method for creating physical connections in 3D integrated circuits	Patent 8732647 was granted and assigned to Atrenta on May, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8732647	May 20, 2014
‌ US Patent 8984457 System and method for a hybrid clock domain crossing verification	Patent 8984457 was granted and assigned to Atrenta on March, 2015 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8984457	March 17, 2015
‌ US Patent 7882483 Method for checking constraints equivalence of an integrated circuit design	Patent 7882483 was granted and assigned to Atrenta on February, 2011 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	7882483	February 1, 2011
‌ US Patent 8677295 Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design	Patent 8677295 was granted and assigned to Atrenta on March, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8677295	March 18, 2014
‌ US Patent 8806401 System and methods for reasonable functional verification of an integrated circuit design	Patent 8806401 was granted and assigned to Atrenta on August, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8806401	August 12, 2014
‌ US Patent 7650581 Method for modeling and verifying timing exceptions	Patent 7650581 was granted and assigned to Atrenta on January, 2010 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	7650581	January 19, 2010
‌ US Patent 8042085 Method for compaction of timing exception paths	Patent 8042085 was granted and assigned to Atrenta on October, 2011 by the United States Patent and Trademark Office.		Atrenta	United States Patent and Trademark Office	8042085	October 18, 2011
‌ US Patent 8856706 System and method for metastability verification of circuits of an integrated circuit	Patent 8856706 was granted and assigned to Atrenta on October, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8856706	October 7, 2014
‌ US Patent 8839171 Method of global design closure at top level and driving of downstream implementation flow	Patent 8839171 was granted and assigned to Atrenta on September, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8839171	September 16, 2014
‌ US Patent 8881075 Method for measuring assertion density in a system of verifying integrated circuit design	Patent 8881075 was granted and assigned to Atrenta on November, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8881075	November 4, 2014
‌ US Patent 8756466 Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test	Patent 8756466 was granted and assigned to Atrenta on June, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8756466	June 17, 2014
‌ US Patent 8656326 Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design	Patent 8656326 was granted and assigned to Atrenta on February, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8656326	February 18, 2014
‌ US Patent 8813003 System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency	Patent 8813003 was granted and assigned to Atrenta on August, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8813003	August 19, 2014
‌ US Patent 8782582 Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis	Patent 8782582 was granted and assigned to Atrenta on July, 2014 by the United States Patent and Trademark Office.	Atrenta	Atrenta	United States Patent and Trademark Office	8782582	July 15, 2014

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