Atrenta

US Patent 7152216 Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains

US Patent 7216321 Pattern recognition in an integrated circuit design

US Patent 7277840 Method for detecting bus contention from RTL description

US Patent 7349835 Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuits

US Patent 7451427 Bus representation for efficient physical synthesis of integrated circuit designs

US Patent 7506292 Method for clock synchronization validation in integrated circuit design

US Patent 7536662 Method for recognizing and verifying FIFO structures in integrated circuit designs

US Patent 7546559 Method of optimization of clock gating in integrated circuit designs

US Patent 7650581 Method for modeling and verifying timing exceptions

US Patent 7712061 Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits

US Patent 7882483 Method for checking constraints equivalence of an integrated circuit design

US Patent 7941679 Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design