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Chuong D. Ngo

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Edits on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7089275 Block-partitioned technique for solving a system of linear equations represented by a matrix with static and dynamic entries
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US Patent 7092979 Random data generator and scrambler using the same, and method therefore
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US Patent 7096241 Exponent encoder circuit and mask circuit
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US Patent 7096243 Flexible decimator
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US Patent 7096245 Inverse discrete cosine transform supporting multiple decoding processes
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US Patent 7099908 Merge and split generalized block transform method
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US Patent 7103624 Comparator circuit and method
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US Patent 7111029 Random number generating circuit
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US Patent 7113968 Method and apparatus for efficiently performing Galois field multiplication
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US Patent 7113969 Formatting denormal numbers for processing in a pipelined floating point unit
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US Patent 7113970 Complex-valued multiplier-and-accumulator
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US Patent 7124153 Frequency converter and methods of use thereof
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US Patent 7124154 Clock divider
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US Patent 7124159 Parallel decimation circuits
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US Patent 7124161 Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices
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US Patent 11175946 Pipelined matrix multiplication at a graphics processing unit
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US Patent 7136889 Method and apparatus for generating high quality real random numbers using a disk drive
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US Patent 7136890 Inverse discrete cosine transform apparatus
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US Patent 7139787 Multiply execution unit for performing integer and XOR multiplication
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US Patent 7143125 Method and apparatus for noise shaping in direct digital synthesis circuits
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US Patent 7143126 Method and apparatus for implementing power of two floating point estimation
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US Patent 7143127 Scaling method by using symmetrical middle-point slope control (SMSC)
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US Patent 7146392 Random number generator
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US Patent 7152082 Audio frequency response processing system
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US Patent 7152083 Jerk limited time delay filter
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US Patent 7152086 Method and arrangement for sample-rate conversion
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US Patent 7152088 SQRT calculator capable of reducing error
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US Patent 7159002 Biquad digital filter operating at maximum efficiency
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US Patent 7165084 Microprocessor with selectivity available random number generator based on self-test result
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US Patent 7165085 Arithmetic circuits for use with the residue number system
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US Patent 7167883 Filter with multipliers operating in ones complement arithmetic
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US Patent 7167887 Circuitry for carrying out square root and division operations
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US Patent 7167890 Multiplier-based processor-in-memory architectures for image and graphics processing
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US Patent 7171436 Partitioned block frequency domain adaptive filter
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US Patent 7171438 Method for recognition of full-word saturating addition and subtraction
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US Patent 7177894 Switching activity reduced coding for low-power digital signal processing circuitry
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US Patent 7185037 Video block transform
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US Patent 7185038 Systems and methods for extracting coherent correlation data
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US Patent 7185040 Apparatus and method for calculation of divisions and square roots
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US Patent 7185041 Circuit and method for high-speed execution of modulo division
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US Patent 7188130 Automatic temporary precision reduction for enhanced compression
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US Patent 7188132 Hadamard transformation method and apparatus
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US Patent 7191199 Method and device for computing an absolute difference
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US Patent 7191201 Arithmetic processing apparatus
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US Patent 7194496 System and method for producing functions for generating pseudo-random bit sequences
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US Patent 7197524 Direct RF sampling for cable applications and other broadband signals
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US Patent 7200630 Inverse fourier transform method, phase characterization method of optical components from transmission and group delay measurements as well as a system for performing the method
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US Patent 7200631 Method and apparatus for determining an inverse square root of a given positive-definite hermitian matrix
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US Patent 7206799 Modular multiplication method and calculating device
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US Patent 7209939 Precision improvement method for the Strassen/Winograd matrix multiplication method
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US Patent 7213043 Sparce-redundant fixed point arithmetic modules
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US Patent 7216141 Computing carry-in bit to most significant bit carry save adder in current stage
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US Patent 7222144 Weight measurement apparatus, method of eliminating noise and method of designing digital filter
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US Patent 7225214 Digital filter realization
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US Patent 7228325 Bypassable adder
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US Patent 7231413 Transposition circuit
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US Patent 7233965 Continuous random number generation method and apparatus
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US Patent 7233966 Method and device for generating an output signal as a mathematical function of an input signal
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US Patent 7233967 Reflection filter
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US Patent 7233968 Fast fourier transform apparatus
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US Patent 7233970 Computational method, system, and apparatus
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US Patent 7236998 System and method for solving a large system of dense linear equations
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US Patent 7237000 Speed of execution of a conditional subtract instruction and increasing the range of operands over which the instruction would be performed correctly
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US Patent 7240085 Faster shift value calculation using modified carry-lookahead adder
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US Patent 7243117 Random number generator and probability generator
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US Patent 7249153 Data compression using Chebyshev transform
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US Patent 7249154 Method and apparatus for producing an exponential signal
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US Patent 7251673 Method for performing integer divisions
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US Patent 7257607 Random number generating apparatus, random number generating method, program for generating random numbers, audio decoder and audio decoding method
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US Patent 7257609 Multiplier and shift device using signed digit representation
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US Patent 7260595 Logic circuit and method for carry and sum generation and method of designing such a logic circuit
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US Patent 7263539 Circuit and method for generating fixed point data with reduced circuit scale
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US Patent 7269616 Transitive processing unit for performing complex operations
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US Patent 7272621 Previous calculation reuse in a calculator
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US Patent 7272623 Methods and apparatus for determining a floating-point exponent associated with an underflow condition or an overflow condition
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US Patent 7277908 Numeric processor, a numeric processing method, and a data processing apparatus or computer program incorporating a numeric processing mechanism
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US Patent 7277909 High speed adder
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US Patent 7281025 Triggered DDS pulse generator architecture
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US Patent 7284025 DDS pulse generator architecture
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US Patent 7284028 Comparator eliminating need for one's complement logic for signed numbers
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US Patent 7284029 4-to-2 carry save adder using limited switching dynamic logic
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US Patent 7290020 Electronic device to calculate and generate linear and non-linear functions
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US Patent 7290023 High performance implementation of exponent adjustment in a floating point design
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US Patent 7296048 Semiconductor circuit for arithmetic processing and arithmetic processing method
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US Patent 7299251 Adaptive filter
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US Patent 7299252 Power saving zero pruning algorithm for fast fourier transform (FFT) circuitry
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US Patent 7302461 Analog delay elements
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US Patent 7305425 Method and device for digital filtering of interpolated values
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US Patent 7313583 Galois field arithmetic unit for use within a processor
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US Patent 7315876 System and method for providing delay line and/or finite impulse response filters using a lossless and dispersion-free transmission line
‌
US Patent 7318078 System and method adapted to facilitate dimensional transform
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US Patent 7321913 Digital multirate filtering
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US Patent 7321915 Method and apparatus for efficient matrix multiplication in a direct sequence CDMA system
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US Patent 7325022 Methods and apparatus for determining approximating polynomials using instruction-embedded coefficients
‌
US Patent 7328228 Mapping pseudo-random numbers to predefined number ranges
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US Patent 7337203 Exponent calculation apparatus and method, and program
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US Patent 7349933 Analog data compression
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US Patent 7363334 Digital signal-processing structure and methodology featuring engine-instantiated, wave-digital-filter componentry, and fabrication thereof
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US Patent 11182129 Random number generation and acquisition method and device
‌
US Patent 7373368 Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication
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US Patent 7383296 Apparatus for fractional RF signal synthesis with phase modulation
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US Patent 7392270 Apparatus and method for reducing the latency of sum-addressed shifters
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US Patent 7392274 Multi-function floating point arithmetic pipeline
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US Patent 7392277 Cascaded domino four-to-two reducer circuit and method
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US Patent 7395287 Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands
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US Patent 7395292 Method for displaying spectral trends in complex signals
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US Patent 7395294 Arithmetic logic unit
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US Patent 7395307 Carry look-ahead circuit and adder using same
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US Patent 7398287 Fast linear feedback shift register engine
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US Patent 7401108 Random noise generator and a method for generating random noise
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US Patent 7403964 Galois field multiplier array for use within a finite field arithmetic unit
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US Patent 7412470 Arithmetic processing apparatus
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US Patent 7412472 Apparatus and method for filtering a signal
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US Patent 7412477 Interpolation of signals from a delay line
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US Patent 7415494 Divider apparatus and associated method
‌
US Patent 7418468 Low-voltage CMOS circuits for analog decoders
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US Patent 7421461 Pipe reference and calculating device
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US Patent 7421462 Method and apparatus for generating a random bit stream
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US Patent 7424506 Architecture and related methods for efficiently performing complex arithmetic
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US Patent 7426528 Method and device for calculating an iterated state for a feedback shift register arrangement
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US Patent 7428565 Logical operation circuit and logical operation device
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US Patent 7430576 Floating point square root provider with embedded status information
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US Patent 7433906 Method of updating a shift register
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US Patent 7433908 Selective-partial-update proportionate normalized least-mean-square adaptive filtering for network echo cancellation
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US Patent 7437392 Transitioning a filter function of a two-port lattice-form planar waveguide optical delay line circuit filter from a start filter function to a target filter function
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US Patent 7440987 16 bit quadrature direct digital frequency synthesizer using interpolative angle rotation
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US Patent 7440990 Methods of factoring and modular arithmetic
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US Patent 7444366 Faster shift value calculation using modified carry-lookahead adder
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US Patent 7447725 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units
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US Patent 7454454 Method and apparatus for efficient calculation of a matrix power series
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US Patent 7457837 System and method for precise calculation of alternative units of measure
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US Patent 7461107 Converter circuit for converting 1-redundant representation of an integer
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US Patent 7461110 Redundancy-free circuits for zero counters
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US Patent 7461113 Reduced complexity adaptive filter
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US Patent 7461114 Fourier transform apparatus
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US Patent 7461115 Modular multiplier
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US Patent 7461116 Emulation of a fixed point operation using a corresponding floating point operation
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US Patent 7461118 Arithmetic logic unit with merged circuitry for comparison, minimum/maximum selection and saturation for signed and unsigned numbers
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US Patent 7464127 Fast fourier transform apparatus
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US Patent 7464129 Circuitry for carrying out a square root operation
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US Patent 7467170 Sample generation method and system for digital simulation processes
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US Patent 7467172 N dimensional non-linear, static, adaptive, digital filter design using D scale non-uniform sampling
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US Patent 7469266 Method and structure for producing high performance linear algebra routines using register block data format routines
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US Patent 7472152 Accommodating fourier transformation attenuation between transform term frequencies
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US Patent 7472153 Method for exploiting bias in factor analysis using constrained alternating least squares algorithms
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US Patent 7480687 Pseudorandom number generator for a stream cipher
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US Patent 7480691 Arithmetic device for multiple precision arithmetic for Montgomery multiplication residue arithmetic
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US Patent 7487195 Method and structure for producing high performance linear algebra routines using composite blocking based on L1 cache size
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US Patent 7487197 Data processing apparatus incorporating a numeric processing mechanism
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US Patent 7487198 Multibit bit adder
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US Patent 7490118 Expanding instruction set using alternate error byte
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US Patent 7506014 Tunable multi-phase-offset direct digital synthesizer
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US Patent 7506015 Generation of a remainder from division of a first polynomial by a second polynomial
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US Patent 7509364 Partial output finite impulse response filter
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US Patent 7509365 Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
‌
US Patent 7512644 Rate multiplication method and rate multiplier
‌
US Patent 7512647 Condensed Galois field computing system
‌
US Patent 7516171 Arithmetic unit and method for data storage and reading
‌
US Patent 11188302 Top value computation on an integrated circuit device
‌
US Patent 11188304 Validating microprocessor performance
‌
US Patent 7526518 Galois field multiplication system and method
‌
US Patent 7539714 Method, apparatus, and instruction for performing a sign operation that multiplies
‌
US Patent 7539718 Method and apparatus for performing Montgomery multiplications
‌
US Patent 7543008 Apparatus and method for providing higher radix redundant digit lookup tables for recoding and compressing function values
‌
US Patent 7543011 Montgomery modular multiplier and method thereof using carry save addition
‌
US Patent 7552154 System and method for statistically separating and characterizing noise which is added to a signal of a machine or a system
‌
US Patent 7552159 Transform calculation device
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US Patent 7555509 Parallel fast Fourier transformation method of concealed-communication type
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US Patent 7555514 Packed add-subtract operation in a microprocessor
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US Patent 7558812 Structures for LUT-based arithmetic in PLDs
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US Patent 7558815 Processing of performance sensitive transforms
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US Patent RE40854 Fast calculation apparatus for carrying out a forward and an inverse transform
‌
US Patent 7562105 Methods and apparatus for generating a delay using a counter
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US Patent 7562106 Multi-value digital calculating circuits, including multipliers
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US Patent 7565388 Logic cell supporting addition of three binary words
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US Patent 7571202 Method and apparatus for digital noise mask filtering
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US Patent 7574466 Method for finding global extrema of a set of shorts distributed across an array of parallel processing elements
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US Patent 7580965 Discrete-time convolution cycle reduction with programmable digital signal processor
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US Patent 7587437 Parallel efficiency calculation method and apparatus
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US Patent 7587444 Data value addition
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US Patent 7590677 Processor with summation instruction using overflow counter
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US Patent 7593978 Processor reduction unit for accumulation of multiple operands with or without saturation
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US Patent 7599976 System and method for cryptographic key generation
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US Patent 7599977 Direct digital synthesizer system and related methods
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US Patent 7606848 Detector in parallel with a logic component
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US Patent 7613758 Method for optimization of Q-Filter kernel parameters
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US Patent 7613761 Haar wavelet transform embedded lossless type II discrete cosine transform
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US Patent 7627622 System and method of curve fitting
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US Patent 7631026 Signal processing method and signal processing circuit
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US Patent 7631027 Efficient multichannel filtering for CDMA modems
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US Patent 7631029 Device and method for detecting a useful signal in a receiver
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US Patent 7634525 Haar wavelet transform embedded lossless type IV discrete cosine transform
‌
US Patent 7634526 Selectable quantization in an encoder
‌
US Patent 7636747 Digital low-pass filter
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US Patent 7640285 Multipurpose arithmetic functional unit
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US Patent 7647367 Apparatus and method for calculating a multiplication
‌
US Patent 7653675 Convolution operation in a multi-mode wireless processing system
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US Patent 7660839 Digital filter having improved overload recovery characteristics
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US Patent 7664810 Microprocessor apparatus and method for modular exponentiation
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US Patent 7668891 Adjustable time accumulator
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US Patent 7668892 Data processing apparatus and method for normalizing a data value
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US Patent 7668894 Computation of power functions using polynomial approximations
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US Patent 7680870 FFT apparatus for high data rate and method thereof
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US Patent 7680874 Adder
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US Patent 7685221 Efficient remainder calculation for even divisors
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US Patent 7689635 Area efficient shift / rotate system
‌
US Patent 7689638 Method and device for determining and outputting the similarity between two data strings
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US Patent 7689639 Complex logarithmic ALU
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US Patent 7693922 Method for preprocessing a signal and method for signal processing
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US Patent 7693927 Data processing system and method
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US Patent 7693928 Galois field linear transformer trellis system
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US Patent 7693930 Asynchronous full adder, asynchronous microprocessor and electronic apparatus
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US Patent 7698352 System and method for converting from scaled binary coded decimal into decimal floating point
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US Patent 7698356 Smart evaluation in computer algebra
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US Patent 7698358 Programmable logic device with specialized functional block
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US Patent 7702704 Random number generating method and semiconductor integrated circuit device
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US Patent 7702708 Frequency/delay synthesizer architecture
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US Patent 7707233 Coverting a number from a first base to a second base
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US Patent 7707235 Free-running numerically-controlled oscillator using complex multiplication with compensation for amplitude variation due to cumulative round-off errors
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US Patent 7707236 Methods and apparatus for an efficient floating point ALU
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US Patent 7711761 Method and system for digital signal processing, program product therefor
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US Patent 7711764 Pipelined real or complex ALU
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US Patent 7716264 Method and apparatus for performing alignment shifting in a floating-point unit
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US Patent 7716267 Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium
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US Patent 7716268 Method and apparatus for providing a processor based nested form polynomial engine
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US Patent 7720898 Apparatus and method for adjusting exponents of floating point numbers
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US Patent 7725517 Methods for spectral image analysis by exploiting spatial simplicity
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US Patent 7725521 Method and apparatus for computing matrix transformations
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US Patent 7734674 Fast fourier transform (FFT) architecture in a multi-mode wireless processing system
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US Patent 7739320 Waveform equalizer, waveform equalization method, and integrated circuit
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US Patent 7743085 Configurable IC with large carry chains
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US Patent 7747666 Parallel filter realization for wideband programmable digital radios
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US Patent 7747668 Product-sum operation circuit and method
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US Patent 7752248 System and method for video processing
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US Patent 7765249 Use of hybrid interconnect/logic circuits for multiplication
‌
US Patent 7774396 Method and device for low delay processing
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US Patent 7774399 Shift-add based parallel multiplication
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US Patent 7774400 Method and system for performing calculation operations and a device
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US Patent 7779060 Method of generating a chaos-based pseudo-random sequence and a hardware generator of chaos-based pseudo random bit sequences
‌
US Patent 7788309 Interleaved comb and integrator filter structures
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US Patent 7788310 Multi-dimensional transform for distributed memory network
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US Patent 7797363 Processor having parallel vector multiply and reduce operations with sequential semantics
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US Patent 7801939 Complex and hypercomplex inclusive interval expression evaluations with stable numeric evaluations and precision efficacy testing
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US Patent 7805476 Extended Haar transform
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US Patent 7805477 Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors
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US Patent 7805478 Montgomery modular multiplier
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US Patent 7805481 Exploitation of topological categorization of chaotic and fractal functions, including field line calculations
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US Patent 7809784 Apparatus and method for calculation of divisions and square roots
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US Patent 7818361 Method and apparatus for performing two's complement multiplication
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US Patent 7827223 Accelerated throughput synchronized word stream cipher, message authenticator and zero-knowledge output random number generator
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US Patent 7831648 Method and computer program for group delay and magnitude equalization with relaxed phase slope constraint
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US Patent 7836115 System and method adapted to facilitate dimensional transform
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US Patent 7840626 Methods for spectral image analysis by exploiting spatial simplicity
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US Patent 7844650 Pulse output direct digital synthesis circuit
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US Patent 7844651 Equalizer, group delay compensation circuit for the equalizer and method of compensating for group delay in the equalizer
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US Patent 7849126 System and method for fast matrix factorization
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US Patent 7853637 Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies
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US Patent 7856467 Integrated circuit including at least one configurable logic cell capable of multiplication
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US Patent 7870176 Method of and apparatus for implementing fast orthogonal transforms of variable size
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US Patent 7870178 Systems and methods for extracting coherent correlation data
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US Patent 7877431 Floating point encoding systems and methods
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US Patent 7890563 Multi-channel sample rate conversion method
‌
US Patent RE42168 Core computer unit
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US Patent 7895251 Random number generating method and random number generating apparatus
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US Patent 7895255 Method and apparatus for performing a multiplication or division operation in an electronic circuit
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US Patent 7899856 Hysteresis for mixed representation of Java BigDecimal objects
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US Patent 7899859 Efficient error-check and exact-check for Newton-Raphson divide and square-root operations
‌
US Patent 7899860 Method and system for high-speed floating-point operations and related computer program product
‌
US Patent 7908310 Multiplier-divider having error offset function
‌
US Patent 7912884 Method and apparatus for implementing finite impulse response filters without the use of multipliers
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US Patent 7912889 Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication
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US Patent 7917559 Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
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US Patent 7917560 Random number test circuit
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US Patent 7917562 Method and system for estimating and applying a step size value for LMS echo cancellers
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US Patent 7921145 Extending a repetition period of a random sequence
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US Patent 7921146 Apparatus, system, and method for interpolating high-dimensional, non-linear data
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US Patent 7921147 Filtering integrated circuit
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US Patent 7925684 Method and apparatus for distributing random elements
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US Patent 7925685 Driver for a function unit parametrized by a number of input variables
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US Patent 7925686 Linear transformation circuit
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US Patent 7925687 Reporting a saturated counter value
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US Patent 7930330 Scaled exponential smoothing
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US Patent 7930336 Large multiplier for programmable logic device
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US Patent 7933940 Cyclic segmented prefix circuits for mesh networks
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US Patent 7933943 Multiplierless FIR digital filter and method of designing the same
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US Patent 7937424 Frequency converter and methods of use thereof
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US Patent 7937427 Digital generation of a chaotic numerical sequence
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US Patent 7941471 Differential approach to current-mode chaos based random number generator
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US Patent 7941472 Serial correlator architecture
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US Patent 7941473 Calculation apparatus and storage medium in which calculation program is stored
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US Patent 7945606 Method and apparatus for evaluating a time varying signal
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US Patent 7945610 Convolution operation circuit
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US Patent 7949697 Bit field operation circuit
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US Patent 7953784 Detection of potential need to use a larger data format in performing floating point operations
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US Patent 7958175 Method and device for generating a random number in a USB (universal serial bus) peripheral
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US Patent 7958178 Finite impulse response filter for a time-synchronized system
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US Patent 7974996 Math coprocessor
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US Patent 7984092 FIR filter process and FIR filter arrangement
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US Patent 7984093 Polyphase filter having a tunable notch for image rejection
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US Patent 7987220 Computing filter coefficients for an equalizer in a communication receiver
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US Patent 7987221 FFT and FHT engine
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US Patent 7991814 Ultra fast circuitry for digital filtering
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US Patent 7991816 Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
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US Patent 7991817 Method and a circuit using an associative calculator for calculating a sequence of non-associative operations
‌
US Patent 8005881 Scalable architecture for rank order filtering
‌
US Patent 8010586 Apparatus and method of generating DBI signal in semiconductor integrated circuit
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US Patent 8010587 Random number generator
Edits on 8 Dec, 2021
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US Patent 8010587 Random number generator
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US Patent 8010586 Apparatus and method of generating DBI signal in semiconductor integrated circuit
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US Patent 8005881 Scalable architecture for rank order filtering
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US Patent 7991814 Ultra fast circuitry for digital filtering
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US Patent 7987220 Computing filter coefficients for an equalizer in a communication receiver
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US Patent 7987221 FFT and FHT engine
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US Patent 7984093 Polyphase filter having a tunable notch for image rejection
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US Patent 7984092 FIR filter process and FIR filter arrangement
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US Patent 7974996 Math coprocessor
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US Patent 7958178 Finite impulse response filter for a time-synchronized system
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US Patent 7949697 Bit field operation circuit
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US Patent 7945610 Convolution operation circuit
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US Patent 7945606 Method and apparatus for evaluating a time varying signal
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US Patent 7941473 Calculation apparatus and storage medium in which calculation program is stored
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US Patent 7941471 Differential approach to current-mode chaos based random number generator

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