Electronic design automation

Electronic Design Automation (EDA) refers to tools used in the design and verification of integrated circuits (ICs), printed circuit boards (PCBs), and electronic systems, in general. EDA consists of software, hardware, and other services for the definition, planning, design, implementation, verification, and the subsequent manufacturing of semiconductor devices, or chips. In 2020, the global EDA industry was valued at $11.5 billion. With a growing demand for complex ICs, the industry is estimated to grow to $18.1 billion by 2026, a 7.7% CAGR forecast.

With the rise of very large scale integration (VLSI) systems and the increasing complexity of ICs and PCBs, EDA software, or electronic computer-aided design (ECAD), ishas become integral to the production of modern electronic systems, which can contain over a billion circuit elements. Before EDA, integrated circuits had to be designed by hand. The earliest EDA tools assisted with drafting the design, followed by tools helping with place and route and functional verification.

The EDA industry is closely related to the semiconductor manufacturing industry, of which the primary providers are semiconductor foundries or fabs. These facilities are owned by either large, vertically integrated semiconductor companies or independently operated independently as “pure-play” manufacturing service providers, with the latter category becoming the dominant business model. Other related industries include the embedded software industry, and increasingly industries such as photonics and micro-mechanical sectors, which are seeing continued miniaturization and integration into electronic systems. EDA companies work closely with vertical users of the technology including consumer, automotive, aerospace, medical, and other industries with specific electronic design needs.

In the 1960s, computer-assisted interactive graphics design systems became commercially available. While these systems primarily targeted markets such as cartography, mechanical, and architectural design, they also found use in the interactive design of IC layouts. The leading companies producing these systems were Applicon, Calma, and Computervision.

Manufacturers began to use geometric methods to make tape for circuit photoplotters, and by the mid-1970s, developers were starting to automate the design process with tools including place and route (P&R).

In 1980, Carver Mead and Lin Conway published Introduction to VLSI Systems, proposing the idea of chip design through programming languages. The publication showed how using IC logic simulation and functional verification improved the design of complex chips. Usingchips—using computers to simulate the performance of ICs before generating the hardware and eliminating the need for manual design.

With the start of the commercial application-specific integrated circuit (ASIC) industry in the early 1980s, the need for tools to automate the simulation, design, and verification of chips became far more widespread. Many new companies formed to serve this need with captive teams at large OEMs leaving to start new enterprises. During this time, the primary focus was on software and special-purpose hardware capable of capturing the design and simulating it. Major companies leading the early EDA industry include Daisy Systems, Mentor Graphics, and Valid Logic.

The first EDA sales exhibition was held at DAC in 1984. Gateway Design Automation introduced a hardware description language, Verilog, in 1986. In 1987, another hardware description language, VHDL, was created using funds from the US Department of defenseDefense.

In 1989, the EDA Consortium (EDAC) was founded “Toto promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy.”

In 2005, the IEEE Council on Electronic Design Automation (CEDA) was established. The council aims to foster design automation of electronic circuits and systems at all levels. CEDA helps to enable the exchange of technical information through publications, conferences, workshops, and volunteer activities. The council also recognizes scientific activities sponsoring numerous awards for individuals with demonstrable impact on the field. It is an organizational unit of IEEE, with seven member societies:

EDA tools are not directly involved in the manufacture of chips,; instead, EDA is primarily a software business. EDA tools use sophisticated and complex software to function primarily in one of three ways to assist with the design and manufacture of chips:

• Simulation—tools that take a description of a proposed circuit and predict its behavior before implementation.
• Design—tools for assembling the circuit elements required to fulfill the proposed functionality.
• Verification—tools determining whether the chip design is connected correctly and deliversdelivering the required performance.

A newer, separate application in EDA is silicon lifecycle management (SLM), monitoring device performance post-manufacture to ensure it performs as expected and is not tampered with.

While EDA products are primarily delivered as software, there are use cases wherein which physical hardware is required. Typically this is for extremely high performance, when a large amount of data must be processed during simulation and verification. In these instances, a dedicated hardware model is preferable to software, reducing the time taken for various tasks. EDA hardware is primarily delivered via emulation and rapid prototypes.

Simulation tools predict the behavior of proposed circuits typically described in a standard hardware description language such as Verilog or VHDL. These tools model the behavior of circuit elements with varying degrees of detail and undergo a range of simulations to predict the performance of the final circuit. The detail required is generally determined by the type of circuit and its intended use. SimulationsSimulation tools can integrate a hardware-assisted approach if a very large amount of data has to be processed.

Verification tools determine if the resulting design (either logical or physical) delivers the required performance. To do this, verification tools incorporate many processes. Physical verification ensures the design is achievable with the given manufacturing requirements. Verification can also compare the implemented circuit to the original description, ensuring it achieves the required functionality. Layout vs. schematic (LVS), is an example of this process. Functional verification uses simulation technology to compare the design's behavior to expectations. All these verification approaches are defined by the inputs provided. Equivalence checking verifies the performance of the circuit algorithmically, without requiring input stimulus.

EDA tools for analog systems are less modular, due to the added complexity of their function and the strong interaction between different parts of the system. Verilog provides a hardware description language for designing analog electronics called Verilog AMS. However, many EDA tools are integrating description language with verification languageslanguages—SystemVerilog, SystemVerilog for example.

The three largest EDA companies are Cadence, Synopsys, and Mentor. In 2017, Siemens acquired the Mentor Graphics company, along with its portfolio of EDA software and services. In 2021, the company branding changed from Mentor to Siemens EDA a part of Siemens Digital Industries Software.

EDA research is most advanced in Europe and America. While the EDA market in China is significant, R&Dresearch and development started relatively late, and the companies involved are small compared to other regions. The most significant EDA companies and research institutes operating in China include Beijing Huada Nine Days Software Co. Ltd., Fudan University, and Xi'an Electronics University of Science and Technology.

The design of integrated circuits has become more modular with semiconductor device manufacturing requiring standardized design descriptions and high-level abstract descriptions compiled into information units. Designers are not required to consider specific hardware technology of the information unit. Instead, specific IC manufacturing processes implement hardware circuitry with the information unit implementing predefined logic or other functionality. Semiconductor manufacturers provide a library of components with corresponding standardized simulation models.

EDA tools for analog systems are less modular due to the added complexity of their function and the strong interaction between different parts of the system. Verilog provides a hardware description language for designing analog electronics called Verilog AMS. However, many EDA tools are integrating description language with verification languages, SystemVerilog for example.

Important users of EDA tools include the hardware technicians at semiconductor manufacturing centers operating equipment and managing facilities. Some design companies also use EDA software to determine whether manufacturing centers can adapt to new designs.

While the use of EDA software remains primarily within the semiconductor industry, new trends associated with digital transformation have seen IC and PCB design in use in broader markets. Within the automotive industry, OEMs are investing in EDA software for the development of next-generation electrified and autonomous vehicles. EDA is becoming more important to aerospace and defense companies as avionics systems grow in complexity. New technologies such as 5G, machine learning, cloud computing, edge computing, and cybersecurity are placing pressure for innovation on semiconductor and electronics suppliers.

The three largest EDA companies are Cadence, Synopsys, and Mentor. In 2017, Siemens acquired the Mentor Graphics company along with its portfolio of EDA software and services. In 2021 the company branding changed from Mentor to Siemens EDA a part of Siemens Digital Industries Software.

EDA research is most advanced in Europe and America. While the EDA market in China is significant, R&D started relatively late and the companies involved are small compared to other regions. The most significant EDA companies and research institutes operating in China include Beijing Huada Nine Days Software Co. Ltd., Fudan University, and Xi'an Electronics University of Science and Technology.

With the rise of very large scale integration (VLSI) systems and the increasing complexity of ICs and PCBs, EDA software, or electronic computer-aided design (ECAD), is essentialintegral forto the production of modern electronic systems, which can contain over a billion circuit elements. Before EDA, integrated circuits had to be designed by hand. The earliest EDA tools assisted with drafting the design, followed by tools helping with place and route and functional verification.

The EDA industry is closely related to the semiconductor manufacturing industry of which the primary providers are semiconductor foundries or fabs. These facilities are owned by either large vertically integrated semiconductor companies or operated independently as “pure-play” manufacturing service providers, with the latter category becoming the dominant business model. Other related industries include the embedded software industry, and increasingly industries such as photonics and micro-mechanical sectors, which are seeing continued miniaturization and integration into electronic systems. EDA companies work closely with vertical users of the technology including consumer, automotive, aerospace, medical, and other industries with specific electronic design needs.

The first EDA sales exhibition was held at the DAC in 1984. Gateway Design Automation introduced hardware description language, Verilog in 1986. In 1987, another hardware description language, VHDL, was created using funds from the US Department of defense.

In 2005, the IEEE Council on Electronic Design Automation (CEDA) was established. The council aims to foster design automation of electronic circuits and systems at all levels. CEDA helps to enable the exchange of technical information through publications, conferences, workshops, and volunteer activities. The council also recognizes scientific activities sponsoring numerous awards for individuals with demonstrable impact on the field. It is an organizational unit of IEEE with seven member societies:

• Antennas and propagation
• Circuits and systems
• Computer
• Electron devices
• Electronics packaging
• Microwave theory and techniques
• Solid-state circuits

Simulation tools predict the behavior of proposed circuits typically described in a standard hardware description language such as Verilog or VHDL. These tools model the behavior of circuit elements with varying degrees of detail and undergo a range of simulations to predict the performance of the final circuit. The detail required is generally determined by the type of circuit and its intended use. Simulations tools can integrate a hardware-assisted approach if a very large amount of data has to be processed.

Design tools assemble the circuit element based on the proposed circuit function. The design process is both a logical (assembling and connecting circuit elements) and physical process (creating the interconnected geometric shapes to implement the circuit during manufacturing). An example of the logical design process is logic synthesis. Generally speaking, the physical design process is known as place and route but can also be an interactive process guided by a designer, known as custom layout.

Verification tools determine if the resulting design (either logical or physical) delivers the required performance. To do this, verification tools incorporate many processes. Physical verification ensures the design is achievable with the given manufacturing requirements. Verification can also compare the implemented circuit to the original description ensuring it achieves the required functionality. Layout vs. schematic (LVS), is an example of this process. Functional verification uses simulation technology to compare the design's behavior to expectations. All these verification approaches are defined by the inputs provided. Equivalence checking verifies the performance of the circuit algorithmically without requiring input stimulus.

Electronic Design Automation (EDA) refers to tools used in the design and verification of integrated circuits (ICs), printed circuit boards (PCBs), and electronic systems, in general. EDA consists of software, hardware, and other services for the definition, planning, design, implementation, verification, and the subsequent manufacturing of semiconductor devices, or chips. In 2020 the global EDA industry was valued at $11.5 billion. With a growing demand for complex ICs, the industry is estimated to grow to $18.1 billion by 2026, a 7.7% CAGR forecast.

Before EDA, integrated circuits were designed by hand. As the size and complexity of the designs grew, automation was required. The earliest EDA tools assisted with drafting the design, followed by tools helping with place and route and functional verification.

The EDA industry is closely related to the semiconductor manufacturing industry of which the primary providers are semiconductor foundries or fabs. These facilities are owned by either large vertically integrated semiconductor companies or operated independently as “pure-play” manufacturing service providers, with the latter category becoming the dominant business model.

Other related industries include the embedded software industry, and increasingly industries such as photonics and micro-mechanical sectors seeing continued miniaturization and integration into electronic systems. EDA companies work closely with vertical users of the technology including consumer, automotive, aerospace, medical, and other industries with specific electronic design needs.

With the rise of very large scale integration (VLSI) systems and the increasing complexity of ICs and PCBs, EDA software, or electronic computer-aided design (ECAD), is essential for the production of modern electronic systems, which can contain over a billion circuit elements. Before EDA, integrated circuits had to be designed by hand. The earliest EDA tools assisted with drafting the design, followed by tools helping with place and route and functional verification.

In 2020 the global EDA industry was valued at $11.5 billion. With a growing demand for complex ICs, the industry is estimated to grow to $18.1 billion by 2026, a 7.7% CAGR forecast.

The EDA industry is closely related to the semiconductor manufacturing industry of which the primary providers are semiconductor foundries or fabs. These facilities are owned by either large vertically integrated semiconductor companies or operated independently as “pure-play” manufacturing service providers, with the latter category becoming the dominant business model. Other related industries include the embedded software industry, and increasingly industries such as photonics and micro-mechanical sectors seeing continued miniaturization and integration into electronic systems. EDA companies work closely with vertical users of the technology including consumer, automotive, aerospace, medical, and other industries with specific electronic design needs.

Manufacturers began to use geometric methods to make tape for circuit photoplotters and by the mid-1970s developers attemptedwere starting to automate the entire design process insteadwith oftools automaticallyincluding completingplace maskand sketchesroute (P&R).

In 1980, Carver Mead and Lin Conway published Introduction to VLSI Systems, proposing the idea of chip design through programming languages. The publication showed how using IC logic simulation and functional verification improved the design of complex chips. Using computers to simulate the performance of ICs before generating the hardware and eliminating the need for manual design.

In 1980, Carver Mead and Lin Conway published Introduction to VLSI Systems, proposing the new idea of chip design through programming languages. The publication showed how using IC logic simulation and functional verification improved the design of complex chips. Using computers to simulate the performance of ICs before generating the hardware and eliminating the need for manual design.

Plus, withWith the start of the commercial application-specific integrated circuit (ASIC) industry in the early 1980s, the need for tools to automate the simulation, design, and verification of chips became far more widespread. Many new companies formed to serve this need with captive teams at large OEMs leaving to start new enterprises. During this time the primary focus was on software and special-purpose hardware capable of capturing the design and simulating it. Major companies leading the early EDA industry include Daisy Systems, Mentor Graphics, and Valid Logic.

SinceThe the early 1980s,first EDA commercialized, with the first sales exhibition was held at the DAC in 1984. Gateway Design Automation introduced hardware description language, Verilog in 1986. In 1987, another hardware description language, VHDL, was created using funds from the US Department of defense.

By the late 1980s, the EDA industry had matured with point-tool companies replacing broad-line suppliers of multiple software and hardware products aimed at automating a larger portion of the IC design process. The leading companies of these solutions were Synopsys, Cadence, and Mentor (now Siemens EDA). It was during this phase that the term EDA was first used.

In 1989 the EDA Consortium (EDAC) was founded “To promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy.”

EDA tools are not directly involved in the manufacture of chips, instead, EDA is primarily a software business. EDA tools use sophisticated and complex software to function primarily in one of three ways to assist with the design and manufacture of chips:

• Simulation—tools that take a description of a proposed circuit and predict its behavior before implementation.
• Design—tools for assembling the circuit elements required to fulfill the proposed functionality.
• Verification—tools determining whether the chip design is connected correctly and delivers the required performance.

A newer separate application in EDA is silicon lifecycle management (SLM), monitoring device performance post-manufacture to ensure it performs as expected and is not tampered with.

While EDA products are primarily delivered as software, there are use cases where physical hardware is required. Typically this is for extremely high performance when a large amount of data must be processed during simulation and verification. In these instances, a dedicated hardware model is preferable to software, reducing the time taken for various tasks. EDA hardware is primarily delivered via emulation and rapid prototypes.

Is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD. (Printed circuit boards and wire wrap both contain specialized discussions of the EDA used for those.)

The term "EDA" is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of electrical engineering. This usage probably originates in the IEEE Design Automation Technical Committee.

Electronic Design Automation (EDA) refers to tools used in the design and verification of integrated circuits (ICs), printed circuit boards (PCBs), and electronic systems, in general. EDA consists of software, hardware, and other services for the definition, planning, design, implementation, verification, and the subsequent manufacturing of semiconductor devices, or chips.

This article describes EDA specifically for electronics, and concentrates on EDA used for designing integrated circuits. The segment of the industry that must use EDA are chip designers at semiconductor companies. Large chips are too complex to design by hand.

Before EDA, integrated circuits were designed by hand. As the size and complexity of the designs grew, automation was required. The earliest EDA tools assisted with drafting the design, followed by tools helping with place and route and functional verification.

The EDA industry is closely related to the semiconductor manufacturing industry of which the primary providers are semiconductor foundries or fabs. These facilities are owned by either large vertically integrated semiconductor companies or operated independently as “pure-play” manufacturing service providers, with the latter category becoming the dominant business model.

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology. (See Moore's Law.) Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.

Other related industries include the embedded software industry, and increasingly industries such as photonics and micro-mechanical sectors seeing continued miniaturization and integration into electronic systems. EDA companies work closely with vertical users of the technology including consumer, automotive, aerospace, medical, and other industries with specific electronic design needs.

In 2020 the global EDA industry was valued at $11.5 billion. With a growing demand for complex ICs, the industry is estimated to grow to $18.1 billion by 2026, a 7.7% CAGR forecast.

Before EDA, integrated circuits were designed by hand, and manually laid out. Some advanced shops used geometric software to generate the tapes for the Gerber photoplotter, but even those copied digital recordings of mechanically-drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually. The best known company from this era was Calma, whose GDSII format survives.

By the mid-70s, developers were starting to automate the design, and not just the drafting. The first placement and routing (Place and route) tools were developed. The proceedings of the Design Automation Conference cover much of this era.

The next era began more or less with the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980. This groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.

The earliest EDA tools were produced academically, and were in the public domain. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used is the Espresso heuristic logic minimizer and Magic.

Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic idea was to use reliable, low-cost, relatively low-technology IC processes, and pack a large number of projects per wafer, with just a few copies of each projects' chips. Cooperating fabricators either donated the processed wafers, or sold them at cost, seeing the program as helpful to their own long-term growth.

1981 marks the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and collectively referred to as DMV. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.

In 1986, Verilog, a popular high-level design language, was first introduced as a hardware description language by Gateway. In 1987, the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.

Many of the EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of the market leaders are rather incestuous amalgamations of many smaller companies. This trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs (the "tool flow").

While early EDA focused on digital circuitry, many new tools incorporate analog design, and mixed systems. This is happening because there is now a trend to place entire electronic systems on a single chip.

Current digital flows are extremely modular (see Integrated circuit design, Design closure, and Design flow (EDA)). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are much less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal.

Before the emergence of EDA, ICs had to be designed and wired manually. EDA began with large OEMs employing teams of software engineers to build the required tools to automate the design, implementation, and verification of the chips they were manufacturing. Examples of these companies include Bell Laboratories, Texas Instruments, Intel, RCA, General Electric, Sony, and Sharp.

In the 1960s computer-assisted interactive graphics design systems became commercially available. While these systems primarily targeted markets such as cartography, mechanical, and architectural design, they also found use in the interactive design of IC layouts. The leading companies producing these systems were Applicon, Calma, and Computervision.

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

In 1964, the Design Automation Conference (DAC) was founded to promote the development of electronic design automation. Still held annually, DAC is the premier conference for the design and automation of electronic systems, offering training, education, exhibits, and networking opportunities for designers, researchers, tool developers, and vendors.

• Design and Architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
• Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
• Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
• Behavioral Synthesis, High Level Synthesis or Algorithmic Synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
• IP cores: provide pre-programmed design elements.
• EDA databases: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.
• Simulation: simulate a circuit's operation so as to verify correctness and performance.
• Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
• Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
• *Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
• *Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
• Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
• Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
• Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalency at the "logical" level.
• Power analysis and optimization: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
• Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent routing of the design, which adds wires to connect the components' signal and power terminals.
• Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
• Transistor layout: (for analog/mixed-signal devices), sometimes called "polygon pushing" – a prepared-schematic is converted into a layout-map showing all layers of the device.
• Design for Manufacturability: tools to help optimize a design to make it as easy and cheap as possible to manufacture.
• Design closure: IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.
• Analysis of substrate coupling.
• Power network design and analysis
• Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
• Design rule checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
• Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
• Layout extraction, RCX – extracts netlists from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
• Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
• Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
• Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
• Mask generation – generation of flat mask image from hierarchical design.
• Manufacturing Test
• Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
• Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design
• Design For Test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
• Technology CAD, or TCAD, simulates and analyses the underlying process technology. Semiconductor process simulation, the resulting dopant profiles, and electrical properties of devices are derived directly from device physics.
• Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

Manufacturers began to use geometric methods to make tape for circuit photoplotters and by the mid-1970s developers attempted to automate the entire design process instead of automatically completing mask sketches.

Largest companies and their histories

Introduction to VLSI Systems, 1980.

In 1980, Carver Mead and Lin Conway published Introduction to VLSI Systems, proposing the new idea of chip design through programming languages. The publication showed how using IC logic simulation and functional verification improved the design of complex chips. Using computers to simulate the performance of ICs before generating the hardware and eliminating the need for manual design.

Well before Electronic Design Automation, the use of computers to help with drafting tasks was well established, and software commercially available. For example, Calma, Applicon, and Computervision, established in the late 1960s, sold digitizing and drafting software used for ICs. Zuken Inc. in Japan, established in 1976, sold similar software for PC boards. While these tools were valuable, they did not help with the design portion of the process, which was still done by hand. Design Automation software was developed in the 70s, in academia and within large companies, but it was not until the early 1980s that software to help with the design portion of the process became commercially available.

Plus, with the start of the commercial application-specific integrated circuit (ASIC) industry in the early 1980s, the need for tools to automate the simulation, design, and verification of chips became far more widespread. Many new companies formed to serve this need with captive teams at large OEMs leaving to start new enterprises. During this time the primary focus was on software and special-purpose hardware capable of capturing the design and simulating it. Major companies leading the early EDA industry include Daisy Systems, Mentor Graphics, and Valid Logic.

In 1981, Mentor Graphics was founded by managers from Tektronix, Daisy Systems was founded largely by developers from Intel, and Valid Logic Systems by designers from Lawrence Livermore National Laboratory and Hewlett Packard. Meanwhile companies such as Calma and Zuken attempted to expand into the design, as well as the drafting, portion of the market.

Since the early 1980s, EDA commercialized, with the first sales exhibition held at the DAC in 1984. Gateway Design Automation introduced hardware description language, Verilog in 1986. In 1987, another hardware description language, VHDL, was created using funds from the US Department of defense.

When EDA started, analysts categorized these companies as a niche within the “computer aided design” market, primarily mechanical design drafting tools for conceptualizing bridges, buildings and automobiles. In a few years these fields diverged, and today no companies specialize in both mechanical and electrical design automation.

By the late 1980s the EDA industry had matured with point-tool companies replacing broad-line suppliers of multiple software and hardware products aimed at automating a larger portion of the IC design process. The leading companies of these solutions were Synopsys, Cadence, and Mentor (now Siemens EDA). It was during this phase that the term EDA was first used.

Cadence Design Systems was founded in the mid 1980s, specializing in physical IC design. Synopsys was founded about the same time frame to productize logic synthesis. Both have grown to be the largest full-line suppliers of EDA tools. Magma Design Automation was founded in 1997 to take advantage of the simplifications possible by building an IC design system from scratch.

Is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD. (Printed circuit boards and wire wrap both contain specialized discussions of the EDA used for those.)

The term "EDA" is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of electrical engineering. This usage probably originates in the IEEE Design Automation Technical Committee.

This article describes EDA specifically for electronics, and concentrates on EDA used for designing integrated circuits. The segment of the industry that must use EDA are chip designers at semiconductor companies. Large chips are too complex to design by hand.

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology. (See Moore's Law.) Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.

Before EDA, integrated circuits were designed by hand, and manually laid out. Some advanced shops used geometric software to generate the tapes for the Gerber photoplotter, but even those copied digital recordings of mechanically-drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually. The best known company from this era was Calma, whose GDSII format survives.

By the mid-70s, developers were starting to automate the design, and not just the drafting. The first placement and routing (Place and route) tools were developed. The proceedings of the Design Automation Conference cover much of this era.

The next era began more or less with the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980. This groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a hundredfold increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were not just easier to lay out, but more correct as well, because their designs could be simulated more thoroughly before construction.

The earliest EDA tools were produced academically, and were in the public domain. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used is the Espresso heuristic logic minimizer and Magic.

Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic idea was to use reliable, low-cost, relatively low-technology IC processes, and pack a large number of projects per wafer, with just a few copies of each projects' chips. Cooperating fabricators either donated the processed wafers, or sold them at cost, seeing the program as helpful to their own long-term growth.

1981 marks the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and collectively referred to as DMV. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.

In 1986, Verilog, a popular high-level design language, was first introduced as a hardware description language by Gateway. In 1987, the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.

Many of the EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of the market leaders are rather incestuous amalgamations of many smaller companies. This trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs (the "tool flow").

While early EDA focused on digital circuitry, many new tools incorporate analog design, and mixed systems. This is happening because there is now a trend to place entire electronic systems on a single chip.

Current digital flows are extremely modular (see Integrated circuit design, Design closure, and Design flow (EDA)). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are much less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal.

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

• Design and Architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
• Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
• Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
• Behavioral Synthesis, High Level Synthesis or Algorithmic Synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
• IP cores: provide pre-programmed design elements.
• EDA databases: databases specialized for EDA applications. Needed since historically general purpose DBs did not provide enough performance.
• Simulation: simulate a circuit's operation so as to verify correctness and performance.
• Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
• Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
• *Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
• *Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
• Clock Domain Crossing Verification (CDC check): Similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
• Formal verification, also model checking: Attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
• Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalency at the "logical" level.
• Power analysis and optimization: optimizes the circuit to reduce the power required for operation, without affecting the functionality.
• Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent routing of the design, which adds wires to connect the components' signal and power terminals.
• Static timing analysis: Analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
• Transistor layout: (for analog/mixed-signal devices), sometimes called "polygon pushing" – a prepared-schematic is converted into a layout-map showing all layers of the device.
• Design for Manufacturability: tools to help optimize a design to make it as easy and cheap as possible to manufacture.
• Design closure: IC design has many constraints, and fixing one problem often makes another worse. Design closure is the process of converging to a design that satisfies all constraints simultaneously.
• Analysis of substrate coupling.
• Power network design and analysis
• Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
• Design rule checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
• Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
• Layout extraction, RCX – extracts netlists from layout, including parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
• Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
• Resolution enhancement techniques, RET – methods of increasing of quality of final photomask.
• Optical proximity correction, OPC – up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
• Mask generation – generation of flat mask image from hierarchical design.
• Manufacturing Test
• Automatic test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.
• Built-in self-test, or BIST – installs self-contained test-controllers to automatically test a logic (or memory) structure in the design
• Design For Test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
• Technology CAD, or TCAD, simulates and analyses the underlying process technology. Semiconductor process simulation, the resulting dopant profiles, and electrical properties of devices are derived directly from device physics.
• Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

Largest companies and their histories

Well before Electronic Design Automation, the use of computers to help with drafting tasks was well established, and software commercially available. For example, Calma, Applicon, and Computervision, established in the late 1960s, sold digitizing and drafting software used for ICs. Zuken Inc. in Japan, established in 1976, sold similar software for PC boards. While these tools were valuable, they did not help with the design portion of the process, which was still done by hand. Design Automation software was developed in the 70s, in academia and within large companies, but it was not until the early 1980s that software to help with the design portion of the process became commercially available.

In 1981, Mentor Graphics was founded by managers from Tektronix, Daisy Systems was founded largely by developers from Intel, and Valid Logic Systems by designers from Lawrence Livermore National Laboratory and Hewlett Packard. Meanwhile companies such as Calma and Zuken attempted to expand into the design, as well as the drafting, portion of the market.

When EDA started, analysts categorized these companies as a niche within the “computer aided design” market, primarily mechanical design drafting tools for conceptualizing bridges, buildings and automobiles. In a few years these fields diverged, and today no companies specialize in both mechanical and electrical design automation.

Cadence Design Systems was founded in the mid 1980s, specializing in physical IC design. Synopsys was founded about the same time frame to productize logic synthesis. Both have grown to be the largest full-line suppliers of EDA tools. Magma Design Automation was founded in 1997 to take advantage of the simplifications possible by building an IC design system from scratch.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).

Prior to the development of EDA, integrated circuits were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a Gerber photoplotter, responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually; the best-known company from this era was Calma, whose GDSII format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first placement and routing tools were developed; as this occurred, the proceedings of the Design Automation Conference catalogued the large majority of the developments of the time.

The next era began following the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980; this groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a considerable increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.

The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used are the Espresso heuristic logic minimizer, responsible for circuit complexity reductions and Magic, a computer-aided design platform. Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes and pack a large number of projects per wafer, with several copies of chips from each project remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost, as they saw the program helpful to their own long-term growth.

1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix and Intel, had pursued EDA internally, with managers and developers beginning to spin out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics and Valid Logic Systems were all founded around this time and collectively referred to as DMV. In 1981, the U.S. Department of Defense additionally began funding of VHDL as a hardware description language. Within a few years, there were many companies specializing in EDA, each with a slightly different emphasis.

The first trade show for EDA was held at the Design Automation Conference in 1984 and in 1986, Verilog, another popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation. Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform logic synthesis.

Main articles: Integrated circuit design, Design closure, and Design flow (EDA)

Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via the utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools.

Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts). Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology. Some users are foundry operators, who operate the semiconductor fabrication facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs or field-programmable gate arrays, customisable integrated circuit designs.

Design flow primarily remains characterised via several primary components; these include:

• High-level synthesis (additionally known as behavioral synthesis or algorithmic synthesis) – The high-level design description (e.g. in C/C++) is converted into RTL or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
• Logic synthesis – The translation of RTL design description (e.g. written in Verilog or VHDL) into a discrete netlist or representation of logic gates.
• Schematic capture – For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.[clarification needed]
• Layout – usually schematic-driven layout, like Layout in Orcad by Cadence, ARES in Proteus

• Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
• Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
• Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
• Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
• Technology CAD simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
• Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

• Functional verification
• Clock domain crossing verification (CDC check): similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
• Formal verification, also model checking: attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
• Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
• Static timing analysis: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
• Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

• Mask data preparation or MDP - The generation of actual lithography photomasks, utilised to physically manufacture the chip.
• Chip finishing which includes custom designations and structures to improve manufacturability of the layout. Examples of the latter are a seal ring and filler structures.
• Producing a reticle layout with test patterns and alignment marks.
• Layout-to-mask preparation that enhances layout data with graphics operations, such as Resolution enhancement techniques or RET – methods for increasing the quality of the final photomask. This also includes Optical proximity correction or OPC – the up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
• Mask generation – The generation of flat mask image from hierarchical design.
• Automatic test pattern generation or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
• Built-in self-test or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design

• Functional safety analysis, systematic computation of failure in time (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
• Functional safety synthesis, add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improves fault detection / fault tolerance. These includes (not limited to), addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (Interface parity, address alignment, beat count)
• Functional safety verification, running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.

Further information: List of EDA companies

PCB layout and schematic for connector design

Market capitalization and company name as of December 2011:

• $5.77 billion – Synopsys
• $4.46 billion – Cadence
• $2.33 billion – Mentor Graphics
• $507 million – Magma Design Automation; Synopsys acquired Magma in February 2012
• NT$6.44 billion – SpringSoft; Synopsys acquired SpringSoft in August 2012
• ¥11.95 billion – Zuken Inc.

Note: EEsof should likely be on this list, but it does not have a market cap as it is the EDA division of Keysight.

Many EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of the market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on digital circuitry; many new tools incorporate analog design and mixed systems. This is happening due to a trend to place entire electronic systems on a single chip.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD),[1] is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).

Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts).[2] Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology.[3] Some users are foundry operators, who operate the semiconductor fabrication facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs or field-programmable gate arrays, customisable integrated circuit designs.

• Chip finishing which includes custom designations and structures to improve manufacturability of the layout. Examples of the latter are a seal ring and filler structures.[4]

Market capitalization and company name as of December 2011:[5]

• $5.77 billion[6] – Synopsys
• $4.46 billion[7] – Cadence
• $507 million – Magma Design Automation; Synopsys acquired Magma in February 2012[8][9]

Note: EEsof should likely be on this list,[10] but it does not have a market cap as it is the EDA division of Keysight.

Many EDA companies acquire small companies with software or other technology that can be adapted to their core business.[11] Most of the market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on digital circuitry; many new tools incorporate analog design and mixed systems.[12] This is happening due to a trend to place entire electronic systems on a single chip.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD),[1] is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).

Prior to the development of EDA, integrated circuits were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a Gerber photoplotter, responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually; the best-known company from this era was Calma, whose GDSII format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first placement and routing tools were developed; as this occurred, the proceedings of the Design Automation Conference catalogued the large majority of the developments of the time.

The next era began following the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980; this groundbreaking text advocated chip design with programming languages that compiled to silicon. The immediate result was a considerable increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. Often the chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.

The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still widely used are the Espresso heuristic logic minimizer, responsible for circuit complexity reductions and Magic, a computer-aided design platform. Another crucial development was the formation of MOSIS, a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes and pack a large number of projects per wafer, with several copies of chips from each project remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost, as they saw the program helpful to their own long-term growth.

1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix and Intel, had pursued EDA internally, with managers and developers beginning to spin out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics and Valid Logic Systems were all founded around this time and collectively referred to as DMV. In 1981, the U.S. Department of Defense additionally began funding of VHDL as a hardware description language. Within a few years, there were many companies specializing in EDA, each with a slightly different emphasis.

The first trade show for EDA was held at the Design Automation Conference in 1984 and in 1986, Verilog, another popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation. Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform logic synthesis.

Main articles: Integrated circuit design, Design closure, and Design flow (EDA)

Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via the utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools.

Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts).[2] Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology.[3] Some users are foundry operators, who operate the semiconductor fabrication facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs or field-programmable gate arrays, customisable integrated circuit designs.

Design flow primarily remains characterised via several primary components; these include:

• High-level synthesis (additionally known as behavioral synthesis or algorithmic synthesis) – The high-level design description (e.g. in C/C++) is converted into RTL or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
• Logic synthesis – The translation of RTL design description (e.g. written in Verilog or VHDL) into a discrete netlist or representation of logic gates.
• Schematic capture – For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.[clarification needed]
• Layout – usually schematic-driven layout, like Layout in Orcad by Cadence, ARES in Proteus

• Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
• Logic simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
• Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
• Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
• Technology CAD simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics.
• Electromagnetic field solvers, or just field solvers, solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the layout extraction above.

• Functional verification
• Clock domain crossing verification (CDC check): similar to linting, but these checks/tools specialize in detecting and reporting potential issues like data loss, meta-stability due to use of multiple clock domains in the design.
• Formal verification, also model checking: attempts to prove, by mathematical methods, that the system has certain desired properties, and that certain undesired effects (such as deadlock) cannot occur.
• Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
• Static timing analysis: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
• Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

• Mask data preparation or MDP - The generation of actual lithography photomasks, utilised to physically manufacture the chip.
• Chip finishing which includes custom designations and structures to improve manufacturability of the layout. Examples of the latter are a seal ring and filler structures.[4]
• Producing a reticle layout with test patterns and alignment marks.
• Layout-to-mask preparation that enhances layout data with graphics operations, such as Resolution enhancement techniques or RET – methods for increasing the quality of the final photomask. This also includes Optical proximity correction or OPC – the up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask.
• Mask generation – The generation of flat mask image from hierarchical design.
• Automatic test pattern generation or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
• Built-in self-test or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design

• Functional safety analysis, systematic computation of failure in time (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
• Functional safety synthesis, add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improves fault detection / fault tolerance. These includes (not limited to), addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (Interface parity, address alignment, beat count)
• Functional safety verification, running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.

Further information: List of EDA companies

PCB layout and schematic for connector design

Market capitalization and company name as of December 2011:[5]

• $5.77 billion[6] – Synopsys
• $4.46 billion[7] – Cadence
• $2.33 billion – Mentor Graphics
• $507 million – Magma Design Automation; Synopsys acquired Magma in February 2012[8][9]
• NT$6.44 billion – SpringSoft; Synopsys acquired SpringSoft in August 2012
• ¥11.95 billion – Zuken Inc.

Note: EEsof should likely be on this list,[10] but it does not have a market cap as it is the EDA division of Keysight.

Many EDA companies acquire small companies with software or other technology that can be adapted to their core business.[11] Most of the market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on digital circuitry; many new tools incorporate analog design and mixed systems.[12] This is happening due to a trend to place entire electronic systems on a single chip.