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edited on 14 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7089477 Interleaved serial concatenation forming turbo-like codes
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US Patent 7089486 Context switching for on-the-fly processing of fragmented frames
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US Patent 7093170 Coding apparatus and decoding apparatus for transmission/storage of information
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US Patent 7096402 Turbo decoder
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US Patent 7096409 Reed-solomon decoder and decoding method for errors and erasures decoding
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US Patent 7096415 System to limit access when calculating network data checksums
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US Patent 7100101 Method and apparatus for concatenated and interleaved turbo product code encoding and decoding
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US Patent 7103825 Decoding error-correcting codes based on finite geometries
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US Patent 7103826 Memory system and controller for same
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US Patent 7103827 Method and apparatus for detecting start position of code sequence, and decoding method and apparatus using the same
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US Patent 7103832 Scalable cyclic redundancy check circuit
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US Patent 7107499 System and method for adjusting a non-return to zero data stream input threshold
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US Patent 7107509 Higher radix Log MAP processor
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US Patent 7111207 Error-correcting communication method and communication apparatus with de-interleaving and rate de-matching
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US Patent 7111228 System and method for performing parity checks in disk storage system
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US Patent 7117400 Memory device with data line steering and bitline redundancy
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US Patent 7120855 Survivor path memory circuit and Viterbi decoder with the same
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US Patent 7120858 Method and device for off-loading message digest calculations
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US Patent 7124344 Error correction coding and decoding apparatuses
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US Patent 7127656 Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates
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US Patent 7127658 Method and encoder for implementing a fully protected multidimensional linear block code
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US Patent 7127660 Method, apparatus and program storage device for correcting a burst of errors together with a random error using shortened cyclic codes
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US Patent 7127662 Method for recording address information on optical recording medium, optical recording medium including address information recorded thereon by the same method, and method for detecting address information recorded on the same optical recording medium
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US Patent 7127667 ACS circuit and viterbi decoder with the circuit
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US Patent 7127669 Redundant path communication methods and systems
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US Patent 7131049 Transmission/reception apparatus and method for packet retransmission in a CDMA mobile communication system
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US Patent 7131054 Apparatus and method for efficient decoder normalization
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US Patent 7134055 Information recording medium on which sector data generated from ECC block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data
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US Patent 7137044 Interleaver and interleaving method in a communication system
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US Patent 7139967 Convolutional decoding
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US Patent 7143318 Identifying systematic errors in a data recording system
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US Patent 7146554 Turbo decoder employing simplified log-map decoding
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US Patent 7149954 Method and system for programmable field statistic for picture cyclic redundancy check (CRC)
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US Patent 7155656 Method and system for decoding of binary shortened cyclic code
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US Patent 7162661 Systematic and random error detection and recovery within processing stages of an integrated circuit
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US Patent 7165205 Method and apparatus for encoding and decoding data
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US Patent 7174484 Data transmission system
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US Patent 7178090 Error correction code decoding device
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US Patent 7181669 Device and method for block code error correction
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US Patent 7181676 Layered decoding approach for low density parity check (LDPC) codes
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US Patent 7185241 Deinterleaving apparatus and method for a digital communication system
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US Patent 7188298 Error correction encoding and decoding methods and apparatuses for DVI audio data
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US Patent 7191385 Error correction in a locating method and system
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US Patent 7191388 Fast diagonal interleaved parity (DIP) calculator
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US Patent 7206962 High reliability memory subsystem using data error correcting code symbol sliced command repowering
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US Patent 7206987 Error detection and correction in a layered, 3-dimensional storage architecture
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US Patent 7210077 System and method for configuring a solid-state storage device with error correction coding
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US Patent 7213191 System and method for securely storing data in a memory
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US Patent 7213192 Methods and apparatus for correcting errors in data read from a disk drive
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US Patent 7216267 Systems and methods for multistage signal detection in mimo transmissions and iterative detection of precoded OFDM
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US Patent 7219289 Multiply redundant raid system and XOR-efficient method and apparatus for implementing the same
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US Patent 7219291 High-speed module, device and method for decoding a concatenated code
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US Patent 7219292 Cyclic redundancy check modification for length detection of message with convolutional protection
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US Patent 7219296 Information reproducing apparatus and method with correction of equalized signal levels
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US Patent 7222284 Low-density parity-check codes for multiple code rates
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US Patent 7222287 Decoder, error position polynomial calculation method, and program
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US Patent 7222290 Method and apparatus for receiver detection on a PCI-Express bus
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US Patent 7225385 Optical recording method
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US Patent 7225388 Error correction encoding and decoding methods and apparatuses for DVI audio data
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US Patent 7231557 Methods and apparatus for interleaving in a block-coherent communication system
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US Patent 7231559 Outage predictor for communication link
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US Patent 7231582 Method and system to encode and decode wide data words
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US Patent 7231587 Embedded picture PSNR/CRC data in compressed video bitstream
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US Patent 7234096 Decoding method and recording-medium reproducing apparatus
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US Patent 7234099 High reliability memory module with a fault tolerant address and command bus
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US Patent 7237171 Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
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US Patent 7237179 Data rate matching device
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US Patent 7240236 Fixed content distributed data storage using permutation ring encoding
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US Patent 7240277 Memory error detection reporting
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US Patent 7243285 Systems and methods for broadcasting information additive codes
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US Patent 7243286 Method and apparatus for generating parity information for error correction
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US Patent 7243288 Method and apparatus for turbo decoding block codes
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US Patent 7246259 Method of calculating parity for surviving dual drive failures in a disk array
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US Patent 7246295 Turbo decoder employing simplified log-map decoding
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US Patent 7246302 Disk player for allocating pointers to frames of CD data and storing pointers in memory and method of processing reproduced data of disk player
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US Patent 7249291 System and method for reliably communicating the content of a live data stream
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US Patent 7249305 Signal processing method and apparatus, signal reproducing method and apparatus, and recording medium
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US Patent 7251768 Wireless communication system having error-control coder and linear precoder
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US Patent 7251769 Methods and apparatus for communication using generalized low density parity check codes
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US Patent 7254755 On-chip receiver sensitivity test mechanism
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US Patent 7257757 Flexible accelerators for physical layer processing
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US Patent 7263651 Method and apparatus for varying lengths of low density party check codewords
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US Patent 7266748 Method and apparatus for correcting C1/PI word errors using error locations detected by EFM/EFM+ decoding
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US Patent 7266760 Method and apparatus for calculating cyclic redundancy checks for variable length packets
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US Patent 7275200 Transparent error correcting memory that supports partial-word write
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US Patent 7275204 Distributed ring control circuits for Viterbi traceback
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US Patent 7278071 Receiving circuit for receiving message signals
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US Patent 7281197 Error-correcting encoding apparatus with variable-rate puncturing
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US Patent 7284179 Window based stall avoidance mechanism for high speed wireless communication system
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US Patent 7284184 Forward error correction scheme compatible with the bit error spreading of a scrambler
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US Patent 7293222 Systems and processes for fast encoding of hamming codes
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US Patent 7296204 Error correction apparatus and method
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US Patent 7296206 Communication device, transmission control method, and program product
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US Patent 7299402 Power control for reverse packet data channel in CDMA systems
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US Patent 7302621 High spread highly randomized generatable interleavers
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US Patent 7302629 Apparatus and method for coding and decoding irregular repeat accumulate codes
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US Patent 7302632 Method and system for the protection of data with a header in a transmission system
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US Patent 7305608 DSL trellis encoding
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US Patent 7318189 Parallel convolutional encoder
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US Patent 7320091 Error recovery within processing stages of an integrated circuit
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US Patent 7320094 Retraining derived clock receivers
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US Patent 7320101 Fast parallel calculation of cyclic redundancy checks
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US Patent 7321995 Coding system and decoding system
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US Patent 7328365 System and method for providing error check and correction in memory systems
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US Patent 7328393 Forward error correction in packet networks
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US Patent 7328395 Iterative Reed-Solomon error-correction decoding
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US Patent 7331013 Viterbi decoder with survivor bits stored to support look-ahead addressing
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US Patent 7337356 Systematic and random error detection and recovery within processing stages of an integrated circuit
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US Patent 7337383 Decisioning rules for turbo and convolutional decoding
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US Patent 7343530 Turbo decoder and turbo interleaver
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US Patent 7343531 Method for interleaving data frame and circuit thereof
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US Patent 7343539 ARA type protograph codes
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US Patent 7346833 Reduced complexity turbo decoding scheme
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US Patent 7350118 Method and apparatus for recording information in concatenated manner
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US Patent 7353438 Transparent error correcting memory
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US Patent 7353444 LDPC architecture
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US Patent 7363533 High reliability memory module with a fault tolerant address and command bus
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US Patent 7363569 Correcting for data losses with feedback and response
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US Patent 7366947 High reliability memory module with a fault tolerant address and command bus
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US Patent 7366963 Data recording/reproduction device, data recording/reproduction method, and digital camera
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US Patent 7366968 Data processing apparatus, and its processing method, program product and mobile telephone apparatus
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US Patent 7370258 Iterative concatenated convolutional Reed-Solomon decoding method
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US Patent 7376880 Transmission apparatus, transmission control program, and transmission method
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US Patent 7380179 High reliability memory module with a fault tolerant address and command bus
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US Patent 7383485 Fast min*- or max*-circuit in LDPC (low density parity check) decoder
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US Patent 7389464 Apparatus and method for encoding and decoding a space-time low density parity check code with full diversity gain
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US Patent 7389465 Error detection and correction scheme for a memory device
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US Patent 7389466 ECC in computer system with associated mass storage device, and method for operating same
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US Patent 7389470 Concatenated equalizer/trellis decoder architecture for an HDTV receiver
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US Patent 7392453 Embedding auxiliary data in an information signal
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US Patent 7392456 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
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US Patent 7392459 Method and apparatus for preventing a false pass of a cyclic redundancy check at a receiver during weak receiving conditions in a wireless communications system
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US Patent 7395463 Electronic apparatus and wireless network system
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US Patent 7398453 Method and apparatus for a low-density parity-check decoder
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US Patent 7401253 Convolution-encoded data storage on a redundant array of independent devices
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US Patent 7401268 Information recording medium on which sector data generated from ECC block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data
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US Patent 7404111 Information recording medium on which sector data generated from ECC block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data
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US Patent 7404134 Encoding/decoding device using a reed-solomon encoder/decoder
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US Patent 7406635 Information recording medium on which sector data generated from ECC block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data
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US Patent 7409606 Method and system for interleaving in a parallel turbo decoder
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US Patent 7409617 System for measuring characteristics of a digital signal
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US Patent 7409627 Method for transmitting and receiving variable length packets based on forward error correction (FEC) coding
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US Patent 7409628 Efficient design to implement LDPC (Low Density Parity Check) decoder
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US Patent 7412641 Protection of data from erasures using subsymbol based codes
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US Patent 7415633 Method and apparatus for preventing and recovering from TLB corruption by soft error
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US Patent 7415661 Early detection of false start-of-packet triggers in a wireless network node
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US Patent 7418644 System for error correction coding and decoding
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US Patent 7421628 Methods and apparatus to extract codes from a plurality of channels
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US Patent 7424667 Digital data transmission error checking method and system
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US Patent 7426676 Data retrieval from a storage device using a combined error correction and detection approach
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US Patent 7428668 Coding system and decoding system using an input code string
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US Patent 7428689 Data memory system and method for transferring data into a data memory
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US Patent 7430703 Error correction for multiple word read
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US Patent 7430706 Diagonal interleaved parity calculator
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US Patent 7434133 Method of retransmitting data frame and network apparatus using the method
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US Patent 7434135 Decoder and method for decoding low-density parity-check code
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US Patent 7434145 Extracting soft information in a block-coherent communication system
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US Patent 7434150 Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations
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US Patent 7437597 Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
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US Patent 7437650 Pre-emptive interleaver address generator for turbo decoders
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US Patent 7441161 Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
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US Patent 7441162 Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
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US Patent 7441176 Method and apparatus for efficiently detecting and/or correcting address information of optical recording/reproducing apparatus
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US Patent 7441177 Information reproduction apparatus and method using maximum likelihood decoding
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US Patent 7441179 Determining a checksum from packet data
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US Patent 7447949 Coding system and decoding system using an input code string
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US Patent 7447977 Method and system for optimizing forward error correction of multimedia streaming over wireless networks
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US Patent 7447978 Buffering packets of a media stream
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US Patent 7451361 Method and apparatus for forward error correction in a content distribution system
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US Patent 7451380 Method for implementing enhanced vertical ECC storage in a dynamic random access memory
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US Patent 7454667 Techniques to provide information validation and transfer
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US Patent 7454669 Coding system and decoding system
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US Patent 7454684 Apparatus and method for turbo decoder termination
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US Patent 7457994 Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
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US Patent 7464304 Coding system and decoding system
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US Patent 7464305 Coding system and decoding system using a synchronization code
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US Patent 7467347 Method for decoding error correcting code, its program and its device
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US Patent 7469364 Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
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US Patent 7469368 Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield
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US Patent 7469373 Application of a Meta-Viterbi algorithm for communication systems without intersymbol interference
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US Patent 7472316 Coding system and decoding system
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US Patent 7472317 Coding system and decoding system
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US Patent 7475298 Coding system and decoding system
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US Patent 7475299 Method and system for real-time bit error ratio determination
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US Patent 7475325 Data processor
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US Patent 7480848 Methods and apparatus to select tornado error correction parameters
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US Patent 7484169 Implicit message sequence numbering for locomotive remote control system wireless communications
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US Patent 7487410 Coding system and decoding system using a multiplexed code string
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US Patent 7487425 Low cost symbol error correction coding and decoding
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US Patent 7487431 Method for a general near optimal turbo code trellis termination
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US Patent 7500172 AMP (accelerated message passing) decoder adapted for LDPC (low density parity check) codes
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US Patent 7500174 Encoding and application of extended hamming checksum
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US Patent 7502985 Method of detecting and correcting errors for a memory and corresponding integrated circuit
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US Patent 7506221 Coding apparatus and decoding apparatus for transmission/storage of information using synchronization code
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US Patent 7506235 Error correction apparatus and method
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US Patent 7506239 Scalable traceback technique for channel decoder
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US Patent 7509526 Method of correcting NAND memory blocks and to a printing device employing the method
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US Patent 7509562 Maintaining data integrity for extended drop outs across high-speed serial links
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US Patent 7512843 Apparatus and method for interleaving channels in a mobile communication system
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US Patent 7512869 Convolutional decoding
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US Patent 7523342 Data and control integrity for transactions in a computer system
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US Patent 7523381 Non-volatile memory with error detection
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US Patent 7526687 Turbo code interleaver with near optimal performance
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US Patent 7526714 Apparatus for checking data coherence, raid controller and storage system having the same, and method therefor
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US Patent 7533306 Turbo decoding apparatus and interleave-deinterleave apparatus
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US Patent 7533331 System and method for securely adding redundancy to an electronic message
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US Patent 7536623 Method and apparatus for generating a low-density parity check code
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US Patent 7536624 Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes
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US Patent 7536628 Decoding apparatus, decoding method and program
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US Patent 7536630 Reconfigurable Viterbi/turbo decoder
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US Patent 7539925 Transmission apparatus and method, reception apparatus and method, storage medium, and program
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US Patent 7539927 High speed hardware implementation of modified Reed-Solomon decoder
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US Patent 7546510 Compact high-speed single-bit error-correction circuit
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US Patent 7552378 Semiconductor device improving error correction processing rate
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US Patent 7552380 Method and apparatus for encoding and decoding modulation code
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US Patent 7559009 System and method for performing parity checks in disk storage systems
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US Patent 7559011 Circuit having a programmable circuit and method of validating a bitstream loaded into a programmable device
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US Patent 7571372 Methods and algorithms for joint channel-code decoding of linear block codes
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US Patent 7574631 Circuit arrangement and method for secure data processing
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US Patent 7577893 Forward error correction decoding method and apparatus for satellite digital audio radio broadcasting
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US Patent 7577899 Cyclic redundancy check (CRC) based error correction method and device
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US Patent 7581160 ACS circuit and Viterbi decoder with the circuit
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US Patent 7581163 Detection of corrupted memory pointers within a packet-processing device
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US Patent 7584408 Viterbi path generation for a Dynamic Bayesian Network
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US Patent 7587641 Encoding of data into constant weight codes
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US Patent 7587653 Decoding method for detecting PLSC from frames of satellite broadcasting system
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US Patent 7587663 Fault detection using redundant virtual machines
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US Patent 7590916 Cyclic redundancy checking value calculator
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US Patent 7590930 Instructions for performing modulo-2 multiplication and bit reflection
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US Patent 7594160 Apparatus and method for receiving signal in a communication system
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US Patent 7600165 Error control coding method and system for non-volatile memory
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US Patent 7600181 Circuit to reduce rail noise voltage spikes due to switching on an input-output bus
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US Patent 7603601 Enabling special modes within a digital device
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US Patent 7607036 System and method for enabling continued use of trim values within an implantable medical device following a parity error
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US Patent 7610542 Semiconductor memory in which error correction is performed by on-chip error correction circuit
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US Patent 7613991 Method and apparatus for concurrent calculation of cyclic redundancy checks
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US Patent 7617434 Adaptive error correction
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US Patent 7620870 Data compression method and system
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US Patent 7620877 Signal decoding methods and apparatus
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US Patent 7627800 Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol
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US Patent 7627801 Methods and apparatus for encoding LDPC codes
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US Patent 7627806 Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device
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US Patent 7631242 System, method and computer program product for mitigating burst noise in a communications system
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US Patent 7631246 LDPC (low density parity check) code size adjustment by shortening and puncturing
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US Patent 7634692 SATA primitive prediction and correction
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US Patent 7634706 Majority-detected erasure enhanced error correction
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US Patent 7644335 In-place transformations with applications to encoding and decoding various classes of codes
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US Patent 7644337 Error correction device, encoder, decoder, method, and information storage device
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US Patent 7644342 Semiconductor memory device
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US Patent 7653858 Low complexity decoding schemes for single-parity-check (SPC) based concatenated codes
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US Patent 7653863 Data storing method for a non-volatile memory cell array having an error correction code
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US Patent 7657797 Turbo code interleaver with near optimal performance
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US Patent 7657816 Low-complexity hybrid LDPC code encoder
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US Patent 7657822 True bit level decoding of TTCM (turbo trellis code modulation) of variable rates and signal constellations
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US Patent 7661037 LDPC concatenation rules for IEEE 802.11n systems
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US Patent 7661057 Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions
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US Patent 7669103 Encoded transmission
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US Patent 7669104 Forward error correction method and communication method, and forward error correction code addition apparatus and communication apparatus
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US Patent 7673192 System and method of uncorrelated code hopping in a communications system
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US Patent 7673224 Low power viterbi decoder using a novel register-exchange architecture
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US Patent 7676726 Stabilization for random chip identifier circuit
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US Patent 7681103 Reliable generation of a device-specific value
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US Patent 7681108 Semiconductor memory module with error correction
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US Patent 7685493 Buffer compression in automatic retransmission request (ARQ) systems
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US Patent 7689893 Iterative reed-solomon error-correction decoding
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US Patent 7707482 Method and device for decoding low-density parity check code and optical information reproducing apparatus using the same
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US Patent 7716536 Techniques for entering a low-power link state
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US Patent 7716538 Memory with cell population distribution assisted read margining
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US Patent 7716551 Feedback and frame synchronization between media encoders and decoders
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US Patent 7716552 Interleaved serial concatenation forming turbo-like codes
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US Patent 7721178 Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code
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US Patent 7725765 Method and apparatus for encryption with RAID in storage system
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US Patent 7730387 Data transmission method and apparatus using multiple scrambling codes
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US Patent 7734982 Method and apparatus for indicating uncorrectable errors to a target
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US Patent 7734988 Method for puncturing a low density parity check code
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US Patent 7734994 RFID decoding subsystem with pre-decode module
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US Patent 7747896 Dual ported replicated data cache
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US Patent 7757151 Turbo decoder employing simplified log-MAP decoding
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US Patent 7761750 Turbo code interleaver with near optimal performance
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US Patent 7761752 Communication terminal device
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US Patent 7761774 High speed CAM lookup using stored encoded key
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US Patent 7761779 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method
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US Patent 7761780 Method, apparatus, and system for protecting memory
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US Patent 7765457 Parallel convolutional encoder
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US Patent 7765458 Error pattern generation for trellis-based detection and/or decoding
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US Patent 7770090 Efficient decoders for LDPC codes
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US Patent 7770097 Redundant path communication methods and systems
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US Patent RE41498 Device and methods for channel coding and rate matching in a communication system
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US Patent 7774652 Circuitry and method to detect conditions of data
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US Patent 7774684 Reliability, availability, and serviceability in a memory device
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US Patent 7779327 Dual stream structure digital television transmission and receiving method using hybrid of E-8VSB, E-4VSB and P2VSB
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US Patent 7779329 Method for a general near optimal turbo code trellis termination
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US Patent 7783957 Apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory
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US Patent 7793172 Controlled reliability in an integrated circuit
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US Patent 7797613 Digital implementation of an enhanced minsum algorithm for error correction in data communications
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US Patent 7797618 Parallel decoder for ultrawide bandwidth receiver
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US Patent 7805642 Low power iterative decoder using input data pipelining and voltage scaling
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US Patent 7805653 LDPC-code generating method, communication apparatus, and code-string generating method
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US Patent 7805658 DRAM Cache with on-demand reload
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US Patent 7805660 Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
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US Patent 7810014 Apparatus and method for stopping iterative decoding in a mobile communication system
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US Patent 7827464 Iterative read channel architectures with coded modulation
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US Patent 7827465 Method for a general near optimal turbo code trellis termination
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US Patent 7836373 Method and apparatus for receiving data in a communication system
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US Patent 7840868 Method of processing traffic information and digital broadcast system
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US Patent 7840885 Distributed ring control circuits for Viterbi traceback
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US Patent 7840887 Data stream processing method and system
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US Patent 7844888 Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit
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US Patent 7849391 Early detection of false start-of-packet triggers in a wireless network node
‌
US Patent 7856579 Network for permutation or de-permutation utilized by channel coding algorithm
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US Patent 7861146 Viterbi decoding apparatus and Viterbi decoding method
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US Patent 7865778 Method and system for detecting synchronization errors in programs
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US Patent 7865812 Apparatus and method for determining a detected punctured position in punctured convolutional codes
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US Patent 7877667 Semiconductor memory
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US Patent 7877669 Non-volatile memory with error detection
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US Patent 7877671 Communication apparatus, communication control method, and computer product
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US Patent 7882417 Semiconductor memory device and memory system including the same
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US Patent 7886185 Creation of a device database and synthesis of device driver information during dissimilar system restore
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US Patent 7895507 Add-compare-select structures using 6-input lookup table architectures
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US Patent 7900122 Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation
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US Patent 7904783 Soft-input soft-output decoder for nonvolatile memory
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US Patent 7904792 Apparatus and method for transmitting/receiving signal in a communication system
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US Patent RE42228 Method and apparatus for using data protection code for data integrity in on-chip memory
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US Patent 7921323 Reconfigurable communications infrastructure for ASIC networks
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US Patent 7921348 Time monitoring of packet retransmissions during soft handover
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US Patent 7925952 Distributed midlet testing
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US Patent 7925954 Techniques for entering a low-power link state
‌
US Patent 7925956 Method and apparatus for encoding and decoding data
‌
US Patent 7925961 Adaptive error correction
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US Patent 7925963 Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes
‌
US Patent 7930612 Error detection and correction scheme for a memory device
‌
US Patent 7937628 Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield
‌
US Patent 7937638 Error correction apparatus and method
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US Patent 7937648 Decoding device, control method, and program
‌
US Patent 7941710 System and method of uncorrelated code hopping in a communications system
‌
US Patent 7941724 Embedded retransmission scheme with cross-packet coding
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US Patent 7941726 Low dimensional spectral concentration codes and direct list decoding
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US Patent 7941730 Memory system
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US Patent 7945835 Method and apparatus for efficiently retransmitting data in wireless network environment
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US Patent 7949922 Test apparatus, shift amount measuring apparatus, shift amount measuring method and diagnostic method
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US Patent 7949927 Error correction method and apparatus for predetermined error patterns
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US Patent 7958408 On-chip receiver sensitivity test mechanism
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US Patent 7966547 Multi-bit error correction scheme in multi-level memory storage system
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US Patent 7966548 Method and system for encoding data using rate-compatible irregular LDPC codes based on edge growth and parity splitting
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US Patent 7971125 Systems and methods for prioritizing error correction data
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US Patent 7975208 Method and apparatus for high speed optical recording
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US Patent 7979766 Architecture for a message bus
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US Patent 7979771 Erasure coding technique for scalable and fault tolerant storage system
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US Patent 7992068 Digital television transmission with error correction
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US Patent 7992076 Method and device of rewriting a primary sector of a sector erasable semiconductor memory means
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US Patent 8006165 Memory controller and semiconductor memory device
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US Patent 8010875 Error correcting code with chip kill capability and power saving enhancement
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US Patent 8010877 Communication apparatus, communication control method, and computer product
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US Patent 8010877 Communication apparatus, communication control method, and computer product
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US Patent 8010875 Error correcting code with chip kill capability and power saving enhancement
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US Patent 8006165 Memory controller and semiconductor memory device
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US Patent 7992068 Digital television transmission with error correction
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US Patent 7979771 Erasure coding technique for scalable and fault tolerant storage system
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US Patent 7979766 Architecture for a message bus
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US Patent 7975208 Method and apparatus for high speed optical recording
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US Patent 7971125 Systems and methods for prioritizing error correction data
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US Patent 7966547 Multi-bit error correction scheme in multi-level memory storage system
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edited on 7 Dec, 2021
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US Patent 7958408 On-chip receiver sensitivity test mechanism
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US Patent 7949927 Error correction method and apparatus for predetermined error patterns
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US Patent 7945835 Method and apparatus for efficiently retransmitting data in wireless network environment
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US Patent 7941726 Low dimensional spectral concentration codes and direct list decoding
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US Patent 7941710 System and method of uncorrelated code hopping in a communications system
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US Patent 7941724 Embedded retransmission scheme with cross-packet coding
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US Patent 7941730 Memory system

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