Tela Innovations, Inc.

US Patent 7814456 Method and system for topography-aware reticle enhancement

US Patent 7823098 Method of designing a digital circuit by correlating different static timing analyzers

US Patent 7842975 Dynamic array architecture

US Patent 7865856 System and method for performing transistor-level static performance analysis using cell-level static analysis tools

US Patent 7888705 Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same

US Patent 7906801 Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions

US Patent 7908578 Methods for designing semiconductor device with dynamic array section

US Patent 7910958 Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment

US Patent 7910959 Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level

US Patent 7917879 Semiconductor device with dynamic array section

US Patent 7917885 Methods for creating primitive constructed standard cells

US Patent 7923757 Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level

US Patent 7932544 Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions

US Patent 7932545 Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers

US Patent 7939443 Methods for multi-wire routing and apparatus implementing same

US Patent 7939898 Diffusion variability control and transistor device sizing using threshold voltage implant

US Patent 7943966 Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment

US Patent 7943967 Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments

US Patent 7948012 Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment

US Patent 7948013 Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch

US Patent 7952119 Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch

US Patent 7956421 Cross-coupled transistor layouts in restricted gate level layout architecture

US Patent 7979811 Intermediate layout for resolution enhancement in semiconductor fabrication

US Patent 7979829 Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods

US Patent 7989847 Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths

US Patent 7989848 Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground

US Patent 7994545 Methods, structures, and designs for self-aligning local interconnects used in integrated circuits