Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Wenbao Wang0
Gabriel Rusaneanu0
Krste Mitric0
Slobodan Milijevic0
Date of Patent
June 26, 2018
0Patent Application Number
150906370
Date Filed
April 5, 2016
0Patent Citations Received
0
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Patent Primary Examiner
Patent abstract
A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).
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