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US Patent 10007639 PLL system with master and slave devices

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
April 5, 2016
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Date of Patent
June 26, 2018
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Patent Application Number
15090637
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Patent Citations Received
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US Patent 11502812 Data protocol over clock line
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US Patent 11747855 Synchronization of a clock generator divider setting and multiple independent component clock divider settings
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US Patent 11777703 Phase transport with frequency translation without a PLL
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US Patent 11863299 Shared communication channel that interleaves 1 PPS signals and messaging
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US Patent 11876607 FSYNC mismatch tracking
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US Patent 11994896 Maintaining the correct time when counter values are transferred between clock domains
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US Patent 12021960 Maintaining a virtual time of day
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US Patent 11502764 FSYNC mismatch tracking
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US Patent 11526193 Maintaining the correct time when counter values are transferred between clock domains
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US Patent 10992301 Circuit and method for generating temperature-stable clocks using ordinary oscillators
•••
Patent Inventor Names
Wenbao Wang
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Gabriel Rusaneanu
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Krste Mitric
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Slobodan Milijevic
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10007639
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Patent Primary Examiner
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Jing-Yih Shyu
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