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US Patent 10037394 Hierarchical timing analysis for multi-instance blocks

Patent 10037394 was granted and assigned to Cadence Design Systems on July, 2018 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Cadence Design Systems
Cadence Design Systems
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Date Filed
June 14, 2016
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Date of Patent
July 31, 2018
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Patent Applicant
Cadence Design Systems
Cadence Design Systems
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Patent Application Number
15182338
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Patent Citations Received
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US Patent 10990733 Shared timing graph propagation for multi-mode multi-corner static timing analysis
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US Patent 11914939 Clock re-convergence pessimism removal through pin sharing during clock tree planning
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US Patent 10534878 Circuit place and route optimization based on path-based timing analysis
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US Patent 10831959 Embedded FPGA timing sign-off
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US Patent 10296700 Multimode circuit place and route optimization
Patent Inventor Names
Pawan Kulshreshtha
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Amit Dhuria
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10037394
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Patent Primary Examiner
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Binh Tat
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