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US Patent 10042588 Electronic device and operating method thereof

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Contents

Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10042588
Date of Patent
August 7, 2018
Patent Application Number
15467374
Date Filed
March 23, 2017
Patent Citations Received
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US Patent 11948635 Memory device current limiter
0
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US Patent 10971680 Multi terminal device stack formation methods
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US Patent 11621293 Multi terminal device stack systems and methods
0
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US Patent 11437099 Memory device current limiter
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US Patent 10347314 Method and apparatus for bipolar memory write-verify
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US Patent 10360962 Memory array with individually trimmable sense amplifiers
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US Patent 10395711 Perpendicular source and bit lines for an MRAM array
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US Patent 10395712 Memory array with horizontal source line and sacrificial bitline per virtual source
...
Patent Primary Examiner
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Richard Elms
Patent abstract

Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.

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