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US Patent 10120023 3D tap and scan port architectures

Patent 10120023 was granted and assigned to Texas Instruments on November, 2018 by the United States Patent and Trademark Office.

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Patent abstract

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

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Patent Citations Received
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US Patent 11762014 3D TAP and scan port architectures
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US Patent 11549983 3D tap and scan port architectures
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US Patent 10884057 3D tap and scan port architectures
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US Patent 10545187 Up control, CSU circuit, scan circuit, up signal contact point
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US Patent 11231461 3D tap and scan port architectures
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US Patent 10261126 3D tap and scan port architectures
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 US Patent 10120023 3D tap and scan port architectures

Infobox
Is a
Patent
Patent
Patent applicant
Texas Instruments
Texas Instruments
Current assignee
Texas Instruments
Texas Instruments
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10120023
Date of patent
November 6, 2018
Patent application number
15991581
Date Filed
May 29, 2018
Patent primary examiner
‌
John J Tabone, Jr.

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