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US Patent 10157680 Sub-block mode for non-volatile memory

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
101576800
Patent Inventor Names
Deepanshu Dutta0
Huai-Yuan Tseng0
Xiang Yang0
Xiaochang Miao0
Date of Patent
December 18, 2018
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Patent Application Number
153854540
Date Filed
December 20, 2016
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Patent Citations Received
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US Patent 11990185 Dynamic word line reconfiguration for NAND structure
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US Patent 10636498 Managing bit-line settling time in non-volatile memory
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US Patent 11587619 Block configuration for memory device with separate sub-blocks
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US Patent 11287989 Dynamic allocation of sub blocks
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US Patent 11972820 Non-volatile memory with tier-wise ramp down after program-verify
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US Patent 12112812 Non-volatile memory with early dummy word line ramp down after precharge
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US Patent 11804268 Methods of operating memory devices based on sub-block positions and related memory system
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US Patent 11829645 Memory system and method of operating the same
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...
Patent Primary Examiner
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Hoai V Ho
0
Patent abstract

Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

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