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US Patent 10157794 Integrated circuit structure with stepped epitaxial region
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Patent
Date Filed
June 19, 2017
Date of Patent
December 18, 2018
Patent Application Number
15626321
Patent Citations
US Patent 10014370 Air gap adjacent a bottom source/drain region of vertical transistor device
US Patent 10008417 Vertical transport fin field effect transistors having different channel lengths
US Patent 10014296 Fin-type field effect transistors with single-diffusion breaks and method
Patent Citations Received
US Patent 11056588 Vertical transport field effect transistor with bottom source/drain
US Patent 11043598 Vertical field effect transistor with low-resistance bottom source-drain contact
US Patent 11756961 Staggered stacked vertical crystalline semiconducting channels
US Patent 11251182 Staggered stacked vertical crystalline semiconducting channels
US Patent 10290549 Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same
US Patent 10541273 Vertical thin film transistors with isolation
US Patent 10777468 Stacked vertical field-effect transistors with sacrificial layer patterning
US Patent 10832970 Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10157794
Patent Primary Examiner
Victoria K. Hall
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