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US Patent 10177031 Subtractive etch interconnects

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
December 23, 2014
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Date of Patent
January 8, 2019
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Patent Application Number
14580259
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Patent Citations Received
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US Patent 10685879 Lithographic alignment of a conductive line to a via
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US Patent 11244897 Back end of line metallization
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US Patent 11270913 BEOL metallization formation
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US Patent 11276607 Selective patterning of vias with hardmasks
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US Patent 11302637 Interconnects including dual-metal vias
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US Patent 11398409 Method of forming a BEOL interconnect structure using a subtractive metal via first process
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US Patent 11908791 Partial subtractive supervia enabling hyper-scaling
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US Patent 11942424 Via patterning for integrated circuits
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US Patent 12020949 Subtractive patterning of interconnect structures
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Patent Inventor Names
Griselda Bonilla
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Ronald G. Filippi
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Samuel S. Choi
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Andrew H. Simon
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Junjing Bao
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Naftali E. Lustig
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10177031
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Patent Primary Examiner
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Shaun M Campbell
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