Patent attributes
A shift register and a display device including the same are provided. The shift register includes a first stage sequentially outputting a gate pulse to first and second gate lines of a pixel array corresponding to a voltage of a first Q node and a second stage sequentially outputting the gate pulse to third and fourth gate lines of the pixel array corresponding to a voltage of a second Q node. The first stage includes a start controller charged with the voltage of the first Q node, a first pull-up transistor increasing a voltage of a first output terminal in response to the voltage of the first Q node and a first gate clock, and a second pull-up transistor increasing a voltage of a second output terminal in response to the voltage of the first Q node and a second gate clock.