Patent attributes
Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.