Patent attributes
A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.
