US Patent 10186510 Vertical gate all around library architecture

A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.