US Patent 10211190 Semiconductor packages having reduced stress

A semiconductor package comprises a lower package, a metal layer on the lower package, a ground member on the metal layer, coupled thereto, and an upper package on the lower package. The upper package comprises a ground pattern on a first insulation pattern. The first insulation pattern is on a bottom surface of the upper package and has a hole through which the ground pattern is exposed. The ground member extends inside the hole and is coupled to the ground pattern.