US Patent 10243043 Self-aligned air gap spacer for nanosheet CMOS devices

A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner spacer liner and an air gap are present. Collectively, each inner spacer liner and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.