US Patent 10388755 Stacked nanosheets with self-aligned inner spacers and metallic source/drain

Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. A metal-doped insulator layer is in contact with sidewalls of the channel layers. The metal-doped insulator layer is annealed to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers. The metal-doped insulator layer is etched back to form inner spacers. Source/drain regions are formed in contact with the metallic layer. The sacrificial layers are etched away and a gate stack is formed on and around the channel layers.