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US Patent 10276237 Semiconductor devices including auxiliary bit lines
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Patent
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Date Filed
August 21, 2017
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Date of Patent
April 30, 2019
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Patent Application Number
15681910
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Patent Citations Received
US Patent 12137568 Hybrid bonding contact structure of three-dimensional memory device
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US Patent 11527547 Hybrid bonding contact structure of three-dimensional memory device
US Patent 10878901 Semiconductor devices including auxiliary bit lines
US Patent 11758732 Hybrid bonding contact structure of three-dimensional memory device
US Patent 11778820 Semiconductor storage device and manufacturing method for semiconductor device
Patent Inventor Names
Joonhee Lee
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Jintaek Park
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Jiyoung Kim
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Seong Soon Cho
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10276237
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Patent Primary Examiner
Long Pham
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