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US Patent 10276676 Methods of forming metal gate isolation
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Patent
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Date Filed
April 27, 2018
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Date of Patent
April 30, 2019
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Patent Application Number
15964557
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Patent Citations Received
US Patent 12132051 Method of manufacturing semiconductor devices and semiconductor devices
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US Patent 11749680 Multi-threshold voltage non-planar complementary metal-oxide-semiconductor devices
US Patent 11349028 Semiconductor device with gate cut structure
US Patent 11374104 Methods of reducing capacitance in field-effect transistors
US Patent 11404555 Metal gates and manufacturing methods thereof
US Patent 11955485 Method of manufacturing semiconductor devices and semiconductor devices
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US Patent 10770559 Gate structure and methods of forming metal gate isolation
US Patent 11605634 Multi-threshold voltage non-planar complementary metal-oxide-semiconductor devices
Patent Inventor Names
Chun-Sheng Liang
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Meng-Fang Hsu
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10276676
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Patent Primary Examiner
J. E. Schoenholtz
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