US Patent 10276779 Top electrode cap structure for embedded memory

The present application relates to a method for forming a top-electrode cap structure on a memory cell. In some embodiments, a method for forming a top-electrode cap structure on a memory cell. The method includes providing a memory cell comprising a top electrode, a bottom electrode, and a resistive memory element sandwiched between the top and bottom electrodes. An etch is performed into an interlayer dielectric (ILD) layer covering the memory cell to form a via opening exposing the top electrode of the memory cell. A getter layer is then formed to line the via opening, and further, over and abutting the top electrode of the memory cell. An oxygen-resistant layer is formed over and abutting the getter layer.