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US Patent 10312131 Semiconductor devices with back surface isolation
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Patent
Date Filed
February 16, 2017
Date of Patent
June 4, 2019
Patent Application Number
15434611
Patent Citations Received
US Patent 12087764 Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation
0
US Patent 11515397 III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer
US Patent 11569374 Implanted isolation for device integration on a common substrate
US Patent 12002878 Implanted isolation for device integration on a common substrate
0
US Patent 11469225 Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10312131
Patent Primary Examiner
Jay C Chang
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