Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Sai-Hooi Yeong0
Wei-Yuan Lu0
Date of Patent
June 18, 2019
0Patent Application Number
156965730
Date Filed
September 6, 2017
0Patent Citations Received
Patent Primary Examiner
Patent abstract
In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.
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