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US Patent 10332986 Formation of inner spacer on nanosheet MOSFET

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Patent abstract

A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

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Patent Inventor Names
Juntao Li0
Kangguo Cheng0
Peng Xu0
Zhenxing Bi0
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Patent Citations Received
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US Patent 11664656 ESD protection for integrated circuit devices
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=103329860
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Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
103329860
Date of Patent
June 25, 2019
0
Patent Application Number
152432460
Date Filed
August 22, 2016
0
Official Website
https://pdfpiw.uspto.gov/.piw?Docid=103329860
Patent Citations Received
‌
US Patent 11368016 ESD protection for integrated circuit devices
0
Patent Primary Examiner
‌
Mohammed R Alam
0
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Patent citations received
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US Patent 11368016 ESD protection for integrated circuit devices
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10332986
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 US Patent 10332986 Formation of inner spacer on nanosheet MOSFET

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10332986
Date of patent
June 25, 2019
Patent application number
15243246
Date Filed
August 22, 2016
Patent primary examiner
‌
Mohammed R Alam

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