US Patent 10388535 Wafer processing method with full edge trimming
Patent 10388535 was granted and assigned to Powertech Technology on August, 2019 by the United States Patent and Trademark Office.
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Patent abstract
A wafer processing method uses a chuck table with smaller diameter than a semiconductor wafer to be processed. A cut through edge trimming is therefore implemented on the periphery of the semiconductor wafer to form a cut through straight side at the periphery and also form a flat portion at the periphery as a positioning means for taping and backside grind processes.
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Patent Inventor Names
Chin-Ta Wu0
Chui-Liang Chiu0
Jen-Tung Tseng0
Kun-Chi Hsu0
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US Patent 10388535 Wafer processing method with full edge trimming
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Is a
Patent applicant
Current assignee
Patent jurisdiction
Patent number
10388535
Date of patent
August 20, 2019
Patent application number
15989203
Date Filed
May 25, 2018
Patent primary examiner
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